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authorFelix Held <felix.held@amd.corp-partner.google.com>2021-09-20 15:12:56 +0200
committerFelix Held <felix-coreboot@felixheld.de>2021-09-21 13:56:32 +0000
commitbc0032a8c20d3dadba3eba65e5b6d03743d70170 (patch)
tree3f30f5ece786e9d6c48c80d8a7c3688860e721a9 /util/crossgcc/Makefile.inc
parenta0b25103574fe0eb112f85fa0099ed4e60841c11 (diff)
soc/amd/picasso/fsp_m_params: use DEV_PTR to check if device is enabled
The aliases are defined in the chipset devicetree, so the device pointers will be available for all boards using this SoC. TEST=None Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4c921575e978bb29e61f35e78ff2a1711acf06a Reviewed-on: https://review.coreboot.org/c/coreboot/+/57780 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
Diffstat (limited to 'util/crossgcc/Makefile.inc')
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