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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2020-11-06 10:56:57 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-11-09 10:22:25 +0000
commit58ce44720aac85381d2524ed520b71dce2c3f99c (patch)
treed1ef0f80754a6e9399296d9734a587172ff13731 /util/crossgcc/.gitignore
parent27ba085334d1482c08b5fd9e628a0f11a0fd9202 (diff)
soc/intel/jasperlake: Enable Intel FIVR RFI settings
We already have RFI UPD settings to mitigate RFI noise issues in platform. These UPDs were not getting filled via devicetree but needed to be filled from fsp_params.c Exporting these UPDs to chip.h will allow OEM/ODMs to fill it directly from devicetree and also allow us to control it based on boards instead of keeping it common across SoCs. BUG=b:171683785 BRANCH=None TEST=Compilation works and we're able to fill UPD from devicetree.Value gets reflected in FSP UPDs. Change-Id: I495cd2294368e6b3035c48b9556a83418d5632de Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47286 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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