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authorFelix Held <felix-coreboot@felixheld.de>2023-03-10 00:03:37 +0100
committerFelix Held <felix-coreboot@felixheld.de>2023-03-23 22:45:35 +0000
commitf0b6255446a44f902da88b0f137652753d831fa4 (patch)
treed6c5f234caad71fcfae3e43458101528e5e061ee /util/chromeos
parent586b1c8da06fe34f91c747440730b31428248b34 (diff)
soc/amd/phoenix: introduce and use pstate_msr bitfield struct
Add the pstate_msr union of a bitfield struct and a raw uint64_t to allow easier access of the bitfields of the P state MSRs and use this bitfield struct in get_pstate_core_freq and get_pstate_core_power. The signature of those two function will be changed in a follow-up commit. PPR #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference as well as the reference code. This patch also adds and uses the cpu_vid_8 bit which is the 9th bit of the voltage ID specified in the SVI3 spec. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia024d32ae75cf2ffbc2a2e86a8b3af3dc6cbad61 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Diffstat (limited to 'util/chromeos')
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