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authorSubrata Banik <subratabanik@google.com>2022-05-23 12:07:32 +0530
committerSubrata Banik <subratabanik@google.com>2022-05-25 18:08:06 +0000
commit6299cecb0d6a23e5ed0a8257baef5e6d354de997 (patch)
tree03022b0fe628511085670fae0460dfb4403470af /util/chromeos/crosfirmware.sh
parentf4ba356420790f463f39de10ec71f9a50c5eac12 (diff)
soc/intel/tigerlake: Drop unused `PCH_DEV_SLOT_LPC` macro
This patch drops the unused `PCH_DEV_SLOT_LPC` macro from the Tiger Lake SoC PCI device list. BUG=none TEST=Able to build and boot volteer, google board. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I27a2f31aa706c4d76e9f0db202422bc129368959 Reviewed-on: https://review.coreboot.org/c/coreboot/+/64588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'util/chromeos/crosfirmware.sh')
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