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authorTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-29 20:37:36 -0500
committerTimothy Pearson <tpearson@raptorengineeringinc.com>2016-03-31 20:00:34 +0200
commitc094d9961144871c472698c41ce634e58abb6a32 (patch)
treed6abf49d3f8897fd45fc56134c0ecbfc8331f35b /util/cbmem
parent3b55602b258e04b82dbb41f3332c5fb7f1b7bd81 (diff)
nb/amd/mct_ddr3: Disable MCE framework during DRAM training
On Family 15h processors, with certain RDIMMs, MCEs are generated as a normal part of DCT startup / DRAM training. Disable sync flood on parity or UC data error until ECC has been enabled. Change-Id: Ife54751ff127ffd59baaad35d3fea14ea01ef505 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14186 Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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