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authorLijian Zhao <lijian.zhao@intel.com>2017-07-11 12:33:22 -0700
committerMartin Roth <martinroth@google.com>2017-07-21 15:55:40 +0000
commit399c022a8c6cba7ad6d75fdf377a690395877611 (patch)
tree44a66a2fa6f7065e8c82289495b2df0e5065e972 /util/cbfstool
parent4cfae2f574c93c5640958fefa9f218c19e11399d (diff)
soc/intel/cannonlake: Add postcar stage support
Initialize postcar frame once finish FSP memoryinit Change-Id: I888d471fa620b7fc9f8975524a31f662e1fc5079 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/20534 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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