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| author | Karthikeyan Ramasubramanian <kramasub@chromium.org> | 2022-02-01 22:29:57 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-10 12:50:19 +0000 |
| commit | 876cfe0ee2c2f4bf14a4846fc648b2c32d98c20d (patch) | |
| tree | 5aac877a0edb7f306910d77d13bad9856f013db0 /util/cbfstool/Makefile | |
| parent | fd07fa20da14370846c41a3bada5dcc8eb9459f1 (diff) | |
spd/lp5: Generate initial SPDs for Sabrina SoC
Mainboards using Sabrina SoC will be using LP5 memory technology.
Generate the initial set of SPDs for the existing LP5 memory parts.
BUG=b:211510456
TEST=util/spd_tools/bin/spd_gen spd/lp5/memory_parts.json lp5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Ibb43f26b36460290341c5ffcad1ef5a2ff1647c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'util/cbfstool/Makefile')
0 files changed, 0 insertions, 0 deletions