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authorKrishna Prasad Bhat <krishna.p.bhat.d@intel.com>2022-02-09 14:55:38 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-02-12 17:25:57 +0000
commitb2e9193231e002b2a3bb33a80d18f76b9abc0a10 (patch)
tree1c822fbfabe9e32c8ac480707ee720afcfcf3a88 /util/cavium/devicetree_convert.py
parentf91538c3eca7529810922ee6f39ff2ea767162fa (diff)
mb/google/nissa: Set half_populated true
Alder Lake N has single memory controller with 64-bit bus width. Alder Lake common meminit block driver considers bus width to be 128-bit and populates the meminit data accordingly. By setting half_populated to true, only the bottom half is populated. Ideally, half_populated is used in platforms with multiple channels to enable only one half of the channel. Alder Lake N has single channel, and it would require for new structures to be defined in meminit block driver for LPx memory configurations. In order to avoid adding new structures, set half_populated to true. This has the same effect as having single channel with 64-bit width. Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61764 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
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