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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-07-28 11:32:21 -0600
committerPaul Fagerburg <pfagerburg@chromium.org>2021-09-20 15:44:09 +0000
commitff8d0e64a7b3b60f646014523054eb96ec919112 (patch)
tree86769f6f84ced80759164b1df5cc5837f2b32a5b /util/board_status
parente186821952ad7e2248d63ba21041fe84f756816e (diff)
soc/intel/jasperlake: Clear RTC_BATTERY_DEAD
Normally for vboot-enabled x86 board, the VBNV region is stored in CMOS and backed up to flash (RW_NVRAM). However, on the very first boot after a flash of the full SPI image (so RW_NVRAM is empty), if RTC_BATTERY_DEAD is set, coreboot persistently requests recovery before FSP-M finishes (which appears to be the current location that RTC_BATTERY_DEAD is cleared on this platform). This is because vbnv_cmos_failed() will still return 1. Therefore, immediately after reading RTC_BATTERY_DEAD, it is cleared. This prevents an infinite boot loop when trying to set the recovery mode bit. Note that this was the behavior for previous generations of Intel PMC programming as well (see southbridge/intel, soc/skylake, soc/broadwell, etc). BUG=b:181678769 Change-Id: Idfaa9a24f7b7fefa4f63ab8e3bc4ee6a0f1faedf Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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