diff options
| author | Ronak Kanabar <ronak.kanabar@intel.com> | 2020-04-27 20:26:53 +0530 |
|---|---|---|
| committer | Karthik Ramasubramanian <kramasub@google.com> | 2020-05-26 21:10:25 +0000 |
| commit | b77b446ca8cbca1a5e56570b94e24a57b9889554 (patch) | |
| tree | cc952ab818a994ce14b771effdd4776c19f8ccad /util/bincfg | |
| parent | e184e39e2ed9ac3f76d2c4f2cc830e335a216e45 (diff) | |
vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2114
The FSP-M/S headers added are generated as per FSP v2114.
Following UPDs are deprecated
- IedSize
- EnableC6Dram
Following UPDs are added
- TurboMode
- PavpEnable
- CnviMode
- CnviBtCore
- PchFivrExtV1p05RailEnabledStates
- PchFivrExtVnnRailSxEnabledStates
- PchFivrVccinAuxRetToLowCurModeVolTranTime
- PchFivrVccinAuxRetToHighCurModeVolTranTime
- PchFivrVccinAuxLowToHighCurModeVolTranTime
- PchLockDownGlobalSmi
- PchLockDownBiosInterface
- PchLockDownBiosLock
BUG=b:155054804
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: TBD
Change-Id: Id9355a1eccfbdc1e9a07b37cb3d8e3de125054d9
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Diffstat (limited to 'util/bincfg')
0 files changed, 0 insertions, 0 deletions