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| author | Raul E Rangel <rrangel@chromium.org> | 2021-04-02 10:27:11 -0600 |
|---|---|---|
| committer | Raul Rangel <rrangel@chromium.org> | 2021-04-05 15:01:50 +0000 |
| commit | 1d0e4930baa5afabdb6d531bbae31a61da7c2f87 (patch) | |
| tree | 9d96646196ee50d9293d8b25120476494148f2ec /util/bincfg/gbe-ich9m.set | |
| parent | a435c3e2eabc59b8a2194f125391e836dda9c05f (diff) | |
soc/amd/common/espi: Add missing eSPI register definitions
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15.
BUG=b:183524609
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e601f767327e0a24a086146623af039388b2e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/bincfg/gbe-ich9m.set')
0 files changed, 0 insertions, 0 deletions