summaryrefslogtreecommitdiff
path: root/util/autoport
diff options
context:
space:
mode:
authorMichał Żygowski <michal.zygowski@3mdeb.com>2022-04-29 13:25:07 +0200
committerMichał Żygowski <michal.zygowski@3mdeb.com>2022-10-05 11:00:36 +0000
commitd02bb67dd62e340bb09b3f629cf60a47a1e1adc8 (patch)
treeb4106bd7904ed68ebea69dd818db745a7531233e /util/autoport
parent598c0dda158bd2062442cbf0b42214d5ed95006f (diff)
drivers/crb: Initialize Intel PTT control area
On newer systems such as Alder Lake it has been noticed that Intel PTT control area is not writable until PTT is switched to ready state. The EDK2 CRB drivers always initialize the command/response buffer address and size registers before invoking the TPM command. See STEP 2 in PtpCrbTpmCommand function in tianocore/edk2/SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2Ptp.c Doing the same in coreboot allowed to perform PTT TPM startup successfully and measure the components to PCRs in ramstage on an Alder Lake S platform. TEST=Enable measured boot and see Intel PTT is started successfully and no errors occur during PCR extends on MSI PRO Z690-A DDR4 WIFI. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia8e473ecc1a520851d6d48ccad9da35c6f91005d Reviewed-on: https://review.coreboot.org/c/coreboot/+/63957 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Diffstat (limited to 'util/autoport')
0 files changed, 0 insertions, 0 deletions