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authorArthur Heymans <arthur@aheymans.xyz>2023-01-30 13:32:44 +0100
committerPaul Fagerburg <pfagerburg@chromium.org>2023-02-04 01:42:43 +0000
commitbc3261f8283ba11c389e8cfcc0089390a133c589 (patch)
tree8c4eae5f1a07b9e4ff28c94ba0b2d79414b1cab2 /util/autoport/sandybridge.go
parentb5df65a9aaee50421913ace6d7a4b35e0ddff676 (diff)
util/autoport: Use chipset.cb references
TESTED with x220 logs. Change-Id: I89023b6c6dd5d985168331fbb12b2fc36fb65dc3 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'util/autoport/sandybridge.go')
-rw-r--r--util/autoport/sandybridge.go6
1 files changed, 3 insertions, 3 deletions
diff --git a/util/autoport/sandybridge.go b/util/autoport/sandybridge.go
index a60018e955..bd7f0f0c30 100644
--- a/util/autoport/sandybridge.go
+++ b/util/autoport/sandybridge.go
@@ -41,9 +41,9 @@ func (i sandybridgemc) Scan(ctx Context, addr PCIDevData) {
PCIController: true,
ChildPCIBus: 0,
PCISlots: []PCISlot{
- PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, additionalComment: "Host bridge"},
- PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, additionalComment: "PEG"},
- PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, additionalComment: "iGPU"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x0, Func: 0}, writeEmpty: true, alias: "host_bridge", additionalComment: "Host bridge"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x1, Func: 0}, writeEmpty: true, alias: "peg10", additionalComment: "PEG"},
+ PCISlot{PCIAddr: PCIAddr{Dev: 0x2, Func: 0}, writeEmpty: true, alias: "igd", additionalComment: "iGPU"},
},
},
},