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| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2022-04-02 10:33:00 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-13 15:12:23 +0000 |
| commit | 37c33052e5c32cfd732b149ec0748614ce5f0178 (patch) | |
| tree | 69854910d97ab509410c2862f116738edb2c33dd /util/autoport/main.go | |
| parent | 4bc2ca522d7ecb86a3d74e318c01082493b896d8 (diff) | |
soc/intel/alderlake: Allow mainboard to configure USB2 Phy power gating
The patch adds mechanism in the Alder Lake SoC code to control PCH
USB2 Phy power gating from brya board variant's devicetree. Please refer
Intel doc#723158 for more information.
BUG=b:221461379
TEST=Build and boot Gimble board
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3d80a3e36c6f8a3c0f174f955b11457752809f4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'util/autoport/main.go')
0 files changed, 0 insertions, 0 deletions