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author | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-12-08 10:43:08 -0700 |
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committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2022-01-06 16:49:00 +0000 |
commit | 40c9c8aa8021348e0fd6916b0e06f21398fb42c9 (patch) | |
tree | d7dce3f047ddfac6e2d707949ac9239654fed8b4 /util/apcb | |
parent | 8d0e77bbd4145e138ff43951c8543cea2c3dfd50 (diff) |
soc/intel/alderlake: Add soc_get_cpu_rp_vw_idx() function
The PMC IPC method used to enable/disable PCIe srcclks uses the
LCAP PN field to distinguish PCH RPs. For CPU RPs, the PMC IPC
command expects the RP number to be its "virtual wire index"
instead. This new function returns this virtual wire index
for each of the CPU PCIe RPs.
BUG=b:197983574
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I5e9710f0d210396f9306b948d9dce8b847300147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'util/apcb')
0 files changed, 0 insertions, 0 deletions