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authorEric Lai <eric_lai@quanta.corp-partner.google.com>2023-06-12 14:27:54 +0800
committerFelix Held <felix-coreboot@felixheld.de>2023-06-20 22:55:13 +0000
commitc1ef4f3356be9440e981e23914bff03a98f1d89e (patch)
tree97e3232e79692f9f14fda9f48bf5065ec0eaba37 /util/apcb/apcb_edit.py
parentb26f0f924ab81e578bdbf725960e0d02643f972e (diff)
arch/x86: Introduce DUMP_SMBIOS_TYPE17 config
DDR5 spd is not supported read by coreboot. But FSP can read it, so print the memory information from smbios type17 dimm information. TEST=check the coreboot log. memory Channel-0-DIMM-0 type is DDR5 memory part number is MTC8C1084S1SC56BG1 memory max speed is 5600 MT/s memory speed is 5200 MT/s memory size is 16384 MiB Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I2b5ca1f4a59598531a6cba500672c2717f2a7b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75756 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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