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author | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-04 00:19:28 +0100 |
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committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-11-13 22:30:29 +0000 |
commit | 50a1072180f05c20ec13d521af6f8930ceabb2c3 (patch) | |
tree | c543067d8a7a77d49e6413a38774a71833c15b46 /util/amdtools/k8-compare-pci-space.pl | |
parent | 99b38a9c2fb3bbf52ad254bfcabc80c2d19d3185 (diff) |
soc/intel/cnl: replace the remains of HeciEnabled by device state in dt
The option `HeciEnabled` was partly replaced by use of the device on/off
state in the devicetree in commit 3de90d1. The option has been removed
from the corresponding boards, so `HeciEnabled` is always 0 and ME
always gets disabled during soc finalize, when `HECI_DISABLE_USING_SMM`
is set.
Replace the option in the finalize function by the same dt state check
that sets the FSP option and drop the remaints of `HeciEnabled`.
Devicetrees still having `HeciEnabled` have been adapted to keep the
current behaviour.
Change-Id: Ib4cca9099b9aa3434552a41fbafca7cf6a0dd0eb
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47195
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'util/amdtools/k8-compare-pci-space.pl')
0 files changed, 0 insertions, 0 deletions