diff options
| author | Zheng Bao <fishbaozi@gmail.com> | 2022-04-03 12:50:07 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-05 17:45:58 +0000 |
| commit | 487d04540b551f2b3253b6f9042c723e5472023f (patch) | |
| tree | 99e5e813d6f63e6ed9593f2687de3a3aba018a6b /util/amdfwtool/amdfwtool.c | |
| parent | ac4332421191cbbca6989292eda1a2763760cbf0 (diff) | |
amdfwtool: Add a macro to set explicitly second gen for old SOCs
It is more reasonable than getting the value from memset.
For the reserved bits, keep them as they were for old SOCs.
Change-Id: I65caa11e835d2ff52bec4b8904057bbced434891
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'util/amdfwtool/amdfwtool.c')
| -rw-r--r-- | util/amdfwtool/amdfwtool.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 80595ddb0d..23273e6c9f 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1383,6 +1383,8 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, } switch (soc_id) { case PLATFORM_STONEYRIDGE: + amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; + amd_romsig->efs_gen.reserved = ~0; amd_romsig->spi_readmode_f15_mod_60_6f = efs_spi_readmode; amd_romsig->fast_speed_new_f15_mod_60_6f = efs_spi_speed; break; @@ -1390,6 +1392,8 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, case PLATFORM_PICASSO: /* amd_romsig->efs_gen introduced after RAVEN/PICASSO. * Leave as 0xffffffff for first gen */ + amd_romsig->efs_gen.gen = EFS_BEFORE_SECOND_GEN; + amd_romsig->efs_gen.reserved = ~0; amd_romsig->spi_readmode_f17_mod_00_2f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_00_2f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1410,6 +1414,7 @@ static int set_efs_table(uint8_t soc_id, embedded_firmware *amd_romsig, case PLATFORM_MENDOCINO: case PLATFORM_SABRINA: amd_romsig->efs_gen.gen = EFS_SECOND_GEN; + amd_romsig->efs_gen.reserved = 0; amd_romsig->spi_readmode_f17_mod_30_3f = efs_spi_readmode; amd_romsig->spi_fastspeed_f17_mod_30_3f = efs_spi_speed; switch (efs_spi_micron_flag) { @@ -1803,7 +1808,6 @@ int main(int argc, char **argv) amd_romsig->imc_entry = 0; amd_romsig->gec_entry = 0; amd_romsig->xhci_entry = 0; - amd_romsig->efs_gen.reserved = 0; if (soc_id != PLATFORM_UNKNOWN) { retval = set_efs_table(soc_id, amd_romsig, efs_spi_readmode, |