diff options
author | Zheng Bao <fishbaozi@gmail.com> | 2022-10-16 20:29:03 +0800 |
---|---|---|
committer | Martin L Roth <gaumless@gmail.com> | 2023-01-22 18:34:21 +0000 |
commit | 8eba6625ce659630f2cc2bffd5ce43aa773f66dc (patch) | |
tree | 3310d96f0d22f4f5099faee5f3ed18397d0e4bbe /util/amdfwtool/amdfwtool.c | |
parent | 295f417a96606873dca18c346ea2940690eeac6c (diff) |
amdfwtool: Add entry types required to support glinda & phoenix SOC
Change-Id: I7565c5eda75b332a48613440d7e4cfb388d5012f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'util/amdfwtool/amdfwtool.c')
-rw-r--r-- | util/amdfwtool/amdfwtool.c | 48 |
1 files changed, 45 insertions, 3 deletions
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index bf1c0b2251..b23ee4701d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -256,6 +256,10 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 1, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_PSP_SMU_FIRMWARE2, .subprog = 2, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_BOOT_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_SOC_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_DEBUG_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_INTERFACE_DRIVER, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_DEBUG_UNLOCK, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_HW_IPCFG, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_WRAPPED_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, @@ -298,15 +302,29 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_DMCU_ISR, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_MSMU, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_SPIROM_CFG, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_FW_MPIO, .level = PSP_BOTH | PSP_BOTH_AB }, - { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH }, + { .type = AMD_FW_MPIO, .level = PSP_LVL2 | PSP_BOTH_AB }, + { .type = AMD_FW_PSP_SMUSCS, .level = PSP_BOTH | PSP_LVL2_AB }, { .type = AMD_FW_DMCUB, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_PSP_BOOTLOADER_AB, .level = PSP_LVL2 | PSP_LVL2_AB }, - { .type = AMD_RIB, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_RIB, .level = PSP_LVL2 | PSP_BOTH_AB }, { .type = AMD_FW_MPDMA_TF, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, { .type = AMD_FW_GMI3_PHY, .level = PSP_BOTH | PSP_BOTH_AB }, { .type = AMD_FW_MPDMA_PM, .level = PSP_BOTH | PSP_BOTH_AB }, + { .type = AMD_FW_AMF_SRAM, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_AMF_DRAM, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_AMF_DRAM, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_FCFG_TABLE, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_AMF_WLAN, .inst = 0, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_AMF_WLAN, .inst = 1, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_AMF_MFD, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_TA_IKEK, .level = PSP_BOTH | PSP_LVL2_AB, .skip_hashing = true }, + { .type = AMD_FW_MPCCX, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_LSDMA, .level = PSP_LVL2 | PSP_LVL2_AB }, + { .type = AMD_FW_C20_MP, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_MINIMSMU, .inst = 0, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_MINIMSMU, .inst = 1, .level = PSP_BOTH | PSP_LVL2_AB }, + { .type = AMD_FW_SRAM_FW_EXT, .level = PSP_LVL2 | PSP_LVL2_AB }, { .type = AMD_FW_INVALID }, }; @@ -364,10 +382,22 @@ amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 0, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 0, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 1, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 1, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 2, .subpr = 1, .level = BDT_BOTH }, @@ -376,10 +406,22 @@ amd_bios_entry amd_bios_table[] = { { .type = AMD_BIOS_PMUD, .inst = 3, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 4, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 4, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 5, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 5, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 6, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 6, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 7, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 7, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 9, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 9, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUI, .inst = 10, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_PMUD, .inst = 10, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 11, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 11, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 12, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 12, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUI, .inst = 13, .subpr = 1, .level = BDT_BOTH }, + { .type = AMD_BIOS_PMUD, .inst = 13, .subpr = 1, .level = BDT_BOTH }, { .type = AMD_BIOS_UCODE, .inst = 0, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 1, .level = BDT_LVL2 }, { .type = AMD_BIOS_UCODE, .inst = 2, .level = BDT_LVL2 }, |