summaryrefslogtreecommitdiff
path: root/tests/mock
diff options
context:
space:
mode:
authorGaggery Tsai <gaggery.tsai@intel.com>2022-09-08 13:42:08 -0700
committerMartin Roth <martin.roth@amd.corp-partner.google.com>2022-09-20 08:00:18 +0000
commit517c5a8c547b4ea330d40e16edc3fe6e849505a0 (patch)
tree4b02a3b6b812a92899ba2faafe91ee07e0ab812b /tests/mock
parent7125318ac454b5e60cfadbe375ce6b8e97706b20 (diff)
soc/intel/alderlake: Add power state thresholds
This patch adds power state 1/2/3 threshold setting interfaces and pass the settings to FSP. BUG=b:229803757 BRANCH=None TEST=Add psi1threshold and psi2threshold to overridetree.cb and enable FSP log to ensure the settings are incorrect. Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Diffstat (limited to 'tests/mock')
0 files changed, 0 insertions, 0 deletions