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| author | Arthur Heymans <arthur@aheymans.xyz> | 2021-04-30 15:10:52 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-05-04 14:04:06 +0000 |
| commit | 808c95056604bf4c33cb5f1246273604d83b7069 (patch) | |
| tree | fc95c18643f50581696e987b7add3bec53f59365 /tests/lib/edid-test.c | |
| parent | f25f0954c38f12603f083e89653265e8d4d60501 (diff) | |
drivers/intel/fsp1_1: Remove verstage compilation units
Only SOC_INTEL_BRASWELL is using FSP1.1. It has too little CAR
available set up by FSP-T to have VBOOT_STARTS_IN_BOOTBLOCK and
therefore verstage is not possible either.
Change-Id: I54361c835055907c2a4414ec26a1495425d4ef09
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52785
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'tests/lib/edid-test.c')
0 files changed, 0 insertions, 0 deletions