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| author | Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> | 2021-12-15 14:24:51 +0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-12-28 09:32:56 +0000 |
| commit | 32992f264f3d022d544c7c675f2572971eb90eaf (patch) | |
| tree | 170ddc76d87ccdb9dbba2d24d883d7090a7c70b6 /tests/device/ddr4-test.c | |
| parent | e226aabf79106b0fa66a79ffed8f63fcb73339a3 (diff) | |
soc/mediatek/mt8186: Adjust usage of SRAM L2C
We use parts of SRAM_L2C as the memory of PRERAM_CBMEM_CONSOLE before
DRAM calibration. When we check cbmem, we found the content of this
memory is unreadable.
The L3 (can be used as SRAM_L2C) is 1MB in total. However the BootROM
has configured only half of L2/L3 cache as SRAM. Therefore, decrease
the size of each SRAM region to fit into the first half of the cache.
BUG=b:207725851
TEST=Bootblock log looked good in `cbmem -c`
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I6041767a1ac0a48ecdda29a0c35d90acf6ad0ef2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Diffstat (limited to 'tests/device/ddr4-test.c')
0 files changed, 0 insertions, 0 deletions