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authorArthur Heymans <arthur@aheymans.xyz>2021-11-10 22:09:58 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-03-02 13:15:12 +0000
commitf879d36551dfa86128a691105dda376db50d0c3c (patch)
treec5993dfe46cf8ef06415575a4c030bcc259f9e46 /tests/device/Makefile.inc
parentc89f252608d87d7db7731fdd9c80b4bed0e33b9b (diff)
device/pci_device.c: Improve pci_bridge_route() readability
Both the secondary and subordinate bus numbers are configured in this function but it's not easy to search for in the tree as the PCI writes are hidden inside a bigger write to 'PCI_PRIMARY_BUS'. Use separate variables and PCI config writes to improve the readability. Change-Id: I3bafd6a2e1d3a0b8d1d43997868a787ce3940ca9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'tests/device/Makefile.inc')
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