This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 72 insertions, 72 deletions

diff --git a/targets/via/epia-m/Config-abuild.lb b/targets/via/epia-m/Config-abuild.lb
index 52c1711bd2..85066ba0d7 100644
--- a/targets/via/epia-m/Config-abuild.lb
+++ b/targets/via/epia-m/Config-abuild.lb
@@ -2,26 +2,26 @@ target VENDOR_MAINBOARD
 mainboard VENDOR/MAINBOARD
 
 option CC="CROSSCC"
-option CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option CONFIG_HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 __LOGLEVEL__
 
-option ROM_SIZE=256*1024
+option CONFIG_ROM_SIZE=256*1024
 
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=64*1024
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0-Normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=64*1024
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0-Fallback"
 	payload __PAYLOAD__
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.512kflash.lb b/targets/via/epia-m/Config.512kflash.lb
index 88d13821ff..0cf7e1c593 100644
--- a/targets/via/epia-m/Config.512kflash.lb
+++ b/targets/via/epia-m/Config.512kflash.lb
@@ -5,25 +5,25 @@ target epia-m.512kflash
 
 mainboard via/epia-m
 
-option  MAXIMUM_CONSOLE_LOGLEVEL=8
-option  DEFAULT_CONSOLE_LOGLEVEL=8
+option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 option  CONFIG_CONSOLE_SERIAL8250=1
 
-option ROM_SIZE=512*1024
+option CONFIG_ROM_SIZE=512*1024
 
 
-option HAVE_OPTION_TABLE=1
+option CONFIG_HAVE_OPTION_TABLE=1
 option CONFIG_ROM_PAYLOAD=1
-option HAVE_FALLBACK_BOOT=1
+option CONFIG_HAVE_FALLBACK_BOOT=1
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-option FALLBACK_SIZE=131072
+option CONFIG_FALLBACK_SIZE=131072
 
 ## Coreboot C code runs at this location in RAM
-option _RAMBASE=0x00004000
+option CONFIG_RAMBASE=0x00004000
 
 #
 ###
@@ -35,8 +35,8 @@ option _RAMBASE=0x00004000
 # Via EPIA M
 #
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -44,12 +44,12 @@ romimage "normal"
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
 	payload ../../../../../lnxieepro100.ebi
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.etherboot.lb b/targets/via/epia-m/Config.etherboot.lb
index 6e59424be8..0ceaf171ec 100644
--- a/targets/via/epia-m/Config.etherboot.lb
+++ b/targets/via/epia-m/Config.etherboot.lb
@@ -5,24 +5,24 @@ target epia-m
 
 mainboard via/epia-m
 
-option  MAXIMUM_CONSOLE_LOGLEVEL=8
-option  DEFAULT_CONSOLE_LOGLEVEL=8
+option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 option  CONFIG_CONSOLE_SERIAL8250=1
 
-option ROM_SIZE=256*1024
+option CONFIG_ROM_SIZE=256*1024
 
-option HAVE_OPTION_TABLE=1
+option CONFIG_HAVE_OPTION_TABLE=1
 option CONFIG_ROM_PAYLOAD=1
-option HAVE_FALLBACK_BOOT=1
+option CONFIG_HAVE_FALLBACK_BOOT=1
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-option FALLBACK_SIZE=131072
+option CONFIG_FALLBACK_SIZE=131072
 
 ## Coreboot C code runs at this location in RAM
-option _RAMBASE=0x00004000
+option CONFIG_RAMBASE=0x00004000
 
 #
 ###
@@ -34,8 +34,8 @@ option _RAMBASE=0x00004000
 # Via EPIA-M
 #
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -43,12 +43,12 @@ romimage "normal"
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
 	payload ../../../../../lnxieepro100.ebi
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.filo.lb b/targets/via/epia-m/Config.filo.lb
index bb5bc62a0e..02313ff15a 100644
--- a/targets/via/epia-m/Config.filo.lb
+++ b/targets/via/epia-m/Config.filo.lb
@@ -5,24 +5,24 @@ target epia-m
 
 mainboard via/epia-m
 
-option  MAXIMUM_CONSOLE_LOGLEVEL=8
-option  DEFAULT_CONSOLE_LOGLEVEL=8
+option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 option  CONFIG_CONSOLE_SERIAL8250=1
 
-option ROM_SIZE=256*1024
+option CONFIG_ROM_SIZE=256*1024
 
-option HAVE_OPTION_TABLE=1
+option CONFIG_HAVE_OPTION_TABLE=1
 option CONFIG_ROM_PAYLOAD=1
-option HAVE_FALLBACK_BOOT=1
+option CONFIG_HAVE_FALLBACK_BOOT=1
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-option FALLBACK_SIZE=131072
+option CONFIG_FALLBACK_SIZE=131072
 
 ## Coreboot C code runs at this location in RAM
-option _RAMBASE=0x00004000
+option CONFIG_RAMBASE=0x00004000
 
 #
 ###
@@ -34,8 +34,8 @@ option _RAMBASE=0x00004000
 # EPIA-M
 #
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -44,8 +44,8 @@ romimage "normal"
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -53,4 +53,4 @@ romimage "fallback"
 	payload ../../../../../../filo.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.lb b/targets/via/epia-m/Config.lb
index 19f26d26cb..2f9d6e1d3d 100644
--- a/targets/via/epia-m/Config.lb
+++ b/targets/via/epia-m/Config.lb
@@ -3,16 +3,16 @@
 target via_epia-m
 mainboard via/epia-m
 
-option  MAXIMUM_CONSOLE_LOGLEVEL=8
-option  DEFAULT_CONSOLE_LOGLEVEL=8
+option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 option  CONFIG_CONSOLE_SERIAL8250=1
 
-option ROM_SIZE=256*1024
+option CONFIG_ROM_SIZE=256*1024
 
 
-option HAVE_OPTION_TABLE=1
+option CONFIG_HAVE_OPTION_TABLE=1
 option CONFIG_ROM_PAYLOAD=1
-option HAVE_FALLBACK_BOOT=1
+option CONFIG_HAVE_FALLBACK_BOOT=1
 #option CONFIG_COMPRESSED_PAYLOAD_NRV2B=1
 option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
 
@@ -21,28 +21,28 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-option FALLBACK_SIZE=131072
+option CONFIG_FALLBACK_SIZE=131072
 
 ## Coreboot C code runs at this location in RAM
-option _RAMBASE=0x00004000
+option CONFIG_RAMBASE=0x00004000
 
 #
 # Via EPIA M
 #
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-#option ROM_IMAGE_SIZE=128*1024
-	option ROM_IMAGE_SIZE=64*1024
+	option CONFIG_USE_FALLBACK_IMAGE=0
+#option CONFIG_ROM_IMAGE_SIZE=128*1024
+	option CONFIG_ROM_IMAGE_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0-Normal"
 	payload $(HOME)/svn/payload.elf
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	#option ROM_IMAGE_SIZE=128*1024
-	option ROM_IMAGE_SIZE=60*1024
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	#option CONFIG_ROM_IMAGE_SIZE=128*1024
+	option CONFIG_ROM_IMAGE_SIZE=60*1024
 	option COREBOOT_EXTRA_VERSION=".0-Fallback"
 	payload $(HOME)/svn/payload.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/via/epia-m/Config.vga.filo b/targets/via/epia-m/Config.vga.filo
index c1f88b0bd9..86b4fb29b9 100644
--- a/targets/via/epia-m/Config.vga.filo
+++ b/targets/via/epia-m/Config.vga.filo
@@ -5,23 +5,23 @@ target epia-m
 
 mainboard via/epia-m
 
-option  MAXIMUM_CONSOLE_LOGLEVEL=8
-option  DEFAULT_CONSOLE_LOGLEVEL=8
+option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
+option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
 option  CONFIG_CONSOLE_SERIAL8250=1
 
-option ROM_SIZE=256*1024
-option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_SIZE=256*1024
+option CONFIG_HAVE_OPTION_TABLE=1
 option CONFIG_ROM_PAYLOAD=1
-option HAVE_FALLBACK_BOOT=1
+option CONFIG_HAVE_FALLBACK_BOOT=1
 
 ###
 ### Compute the location and size of where this firmware image
 ### (coreboot plus bootloader) will live in the boot rom chip.
 ###
-option FALLBACK_SIZE=0x18000
+option CONFIG_FALLBACK_SIZE=0x18000
 
 ## Coreboot C code runs at this location in RAM
-option _RAMBASE=0x00004000
+option CONFIG_RAMBASE=0x00004000
 
 ###
 ### Compute the start location and size size of
@@ -32,19 +32,19 @@ option _RAMBASE=0x00004000
 # EPIA-M
 #
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0xc000
-	option ROM_SECTION_OFFSET=0x10000
-	option ROM_SECTION_SIZE=0x18000
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0xc000
+	option CONFIG_ROM_SECTION_OFFSET=0x10000
+	option CONFIG_ROM_SECTION_SIZE=0x18000
 	option COREBOOT_EXTRA_VERSION=".0-Normal"
 	payload $(HOME)/svn/filo.elf
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0xc000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0xc000
 	option COREBOOT_EXTRA_VERSION=".0-Fallback"
 	payload $(HOME)/svn/filo.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"