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authorPatrick Georgi <patrick.georgi@coresystems.de>2010-02-07 21:43:48 +0000
committerPatrick Georgi <patrick.georgi@coresystems.de>2010-02-07 21:43:48 +0000
commitabf2ad716daff751d75907d47bcae4a7044fd7b4 (patch)
treef82427b43d76a4791253373affed1af8669e2e7b /targets/artecgroup/dbe61
parent389240f288b2708617a35ebe8d7f89b3bff316c5 (diff)
newconfig is no more.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'targets/artecgroup/dbe61')
-rw-r--r--targets/artecgroup/dbe61/Config.lb32
1 files changed, 0 insertions, 32 deletions
diff --git a/targets/artecgroup/dbe61/Config.lb b/targets/artecgroup/dbe61/Config.lb
deleted file mode 100644
index eaa979c6f5..0000000000
--- a/targets/artecgroup/dbe61/Config.lb
+++ /dev/null
@@ -1,32 +0,0 @@
-# Config file for the ThinCan dbe61
-
-target dbe61
-mainboard artecgroup/dbe61
-
-# HACK to get the right TSC support.
-option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
-
-option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
-option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
-
-## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
-## (normal AND fallback images and payloads).
-## leave 36k for vsa and 32K for video ROM
-#option CONFIG_ROM_SIZE = 1024*256 - 36*1024 - 32 * 1024
-
-#No VGA for now
-option CONFIG_ROM_SIZE = 1024*512 - 36*1024
-
-# CONFIG_ROM_IMAGE_SIZE is the maximum number of bytes allowed for a coreboot image,
-## not including any payload.
-option CONFIG_ROM_IMAGE_SIZE=64*1024
-
-option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
-option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
-romimage "fallback"
- option CONFIG_USE_FALLBACK_IMAGE=1
- option COREBOOT_EXTRA_VERSION=".0Fallback"
- payload ../payload.elf
-end
-
-buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"