This patch unifies the use of config options in v2 to all start with CONFIG_

It's basically done with the following script and some manual fixup:

VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
	find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

14 files changed, 161 insertions, 161 deletions

diff --git a/targets/amd/db800/Config.lb b/targets/amd/db800/Config.lb
index f1455a0fad..a9230f01bd 100644
--- a/targets/amd/db800/Config.lb
+++ b/targets/amd/db800/Config.lb
@@ -30,20 +30,20 @@ option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
 
 # Leave 36k for VSA.
-option ROM_SIZE=512*1024-36*1024
-# option ROM_SIZE=256*1024-36*1024
-option FALLBACK_SIZE=ROM_SIZE
+option CONFIG_ROM_SIZE=512*1024-36*1024
+# option CONFIG_ROM_SIZE=256*1024-36*1024
+option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
 
-option DEFAULT_CONSOLE_LOGLEVEL = 9
-option MAXIMUM_CONSOLE_LOGLEVEL = 9
-# option DEFAULT_CONSOLE_LOGLEVEL = 4
-# option MAXIMUM_CONSOLE_LOGLEVEL = 4
+option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
+# option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
+# option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
 
 romimage "fallback"
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=64*1024
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload ../payload.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/amd/dbm690t/Config-abuild.lb b/targets/amd/dbm690t/Config-abuild.lb
index ec05545ff7..e299413a2d 100644
--- a/targets/amd/dbm690t/Config-abuild.lb
+++ b/targets/amd/dbm690t/Config-abuild.lb
@@ -4,27 +4,27 @@ target VENDOR_MAINBOARD
 mainboard VENDOR/MAINBOARD
 
 option CC="CROSSCC"
-option CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option CONFIG_HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 __LOGLEVEL__
 
-option ROM_SIZE=1024*1024
+option CONFIG_ROM_SIZE=1024*1024
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
         option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "failover"
-        option USE_FALLBACK_IMAGE=1
-        option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+        option CONFIG_USE_FALLBACK_IMAGE=1
+        option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-failover"
 	payload __PAYLOAD__
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "failover"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover"
diff --git a/targets/amd/dbm690t/Config.lb b/targets/amd/dbm690t/Config.lb
index c0c3f22595..80c9db639d 100644
--- a/targets/amd/dbm690t/Config.lb
+++ b/targets/amd/dbm690t/Config.lb
@@ -4,18 +4,18 @@ target dbm690t
 mainboard amd/dbm690t
 
 romimage "normal"
-	option ROM_SIZE = 1024*1024 - 55808
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+	option CONFIG_ROM_SIZE = 1024*1024 - 55808
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/norwich/Config.lb b/targets/amd/norwich/Config.lb
index 4f4100af3f..5f927c567a 100644
--- a/targets/amd/norwich/Config.lb
+++ b/targets/amd/norwich/Config.lb
@@ -30,20 +30,20 @@ option CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
 option CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
 option CONFIG_COMPRESSED_PAYLOAD_LZMA=0
 
-option ROM_SIZE=512*1024-36*1024
-#option ROM_SIZE=256*1024-36*1024
-option FALLBACK_SIZE=ROM_SIZE
+option CONFIG_ROM_SIZE=512*1024-36*1024
+#option CONFIG_ROM_SIZE=256*1024-36*1024
+option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
 
-option DEFAULT_CONSOLE_LOGLEVEL = 9
-option MAXIMUM_CONSOLE_LOGLEVEL = 9
-#option DEFAULT_CONSOLE_LOGLEVEL = 4
-#option MAXIMUM_CONSOLE_LOGLEVEL = 4
+option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 9
+option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 9
+#option CONFIG_DEFAULT_CONSOLE_LOGLEVEL = 4
+#option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL = 4
 
 romimage "fallback"
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=64*1024
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=64*1024
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload ../payload.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/amd/pistachio/Config-abuild.lb b/targets/amd/pistachio/Config-abuild.lb
index ec05545ff7..e299413a2d 100644
--- a/targets/amd/pistachio/Config-abuild.lb
+++ b/targets/amd/pistachio/Config-abuild.lb
@@ -4,27 +4,27 @@ target VENDOR_MAINBOARD
 mainboard VENDOR/MAINBOARD
 
 option CC="CROSSCC"
-option CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option CONFIG_HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 __LOGLEVEL__
 
-option ROM_SIZE=1024*1024
+option CONFIG_ROM_SIZE=1024*1024
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
         option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "failover"
-        option USE_FALLBACK_IMAGE=1
-        option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+        option CONFIG_USE_FALLBACK_IMAGE=1
+        option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-failover"
 	payload __PAYLOAD__
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "failover"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "failover"
diff --git a/targets/amd/pistachio/Config.lb b/targets/amd/pistachio/Config.lb
index af8e1afa40..e2e7939ac7 100644
--- a/targets/amd/pistachio/Config.lb
+++ b/targets/amd/pistachio/Config.lb
@@ -4,18 +4,18 @@ target pistachio
 mainboard amd/pistachio
 
 romimage "normal"
-	option ROM_SIZE = 1024*1024 - 55808
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+	option CONFIG_ROM_SIZE = 1024*1024 - 55808
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x20000
-	option XIP_ROM_SIZE=0x20000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+	option CONFIG_XIP_ROM_SIZE=0x20000
 	payload ../payload.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/rumba/Config.lb b/targets/amd/rumba/Config.lb
index ee30902b8b..ac42dd41e9 100644
--- a/targets/amd/rumba/Config.lb
+++ b/targets/amd/rumba/Config.lb
@@ -4,11 +4,11 @@
 target rumba
 mainboard amd/rumba
 
-option ROM_SIZE=256*1024
+option CONFIG_ROM_SIZE=256*1024
 
 romimage "normal"
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -19,8 +19,8 @@ romimage "normal"
 end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -30,4 +30,4 @@ romimage "fallback"
 	payload /tmp/filo.elf
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/rumba/Config.nofallback.lb b/targets/amd/rumba/Config.nofallback.lb
index 448df55652..d3c5464882 100644
--- a/targets/amd/rumba/Config.nofallback.lb
+++ b/targets/amd/rumba/Config.nofallback.lb
@@ -4,13 +4,13 @@
 target rumba
 mainboard amd/rumba
 
-option ROM_SIZE=128*1024
-option FALLBACK_SIZE=ROM_SIZE
-#option FALLBACK_SIZE=65535
+option CONFIG_ROM_SIZE=128*1024
+option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
+#option CONFIG_FALLBACK_SIZE=65535
 
 #romimage "normal"
-#	option USE_FALLBACK_IMAGE=0
-#	option ROM_IMAGE_SIZE=0x10000
+#	option CONFIG_USE_FALLBACK_IMAGE=0
+#	option CONFIG_ROM_IMAGE_SIZE=0x10000
 #	option COREBOOT_EXTRA_VERSION=".0Normal"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -21,8 +21,8 @@ option FALLBACK_SIZE=ROM_SIZE
 #end
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x10000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 #	payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
 #	payload ../../../../tg3--ide_disk.zelf	
@@ -33,6 +33,6 @@ romimage "fallback"
 #	payload /home/ollie/work/filo-0.4.1/filo.elf
 end
 
-#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback"
-buildrom ./coreboot.rom ROM_SIZE "fallback"
+#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
 
diff --git a/targets/amd/serengeti_cheetah/Config-abuild.lb b/targets/amd/serengeti_cheetah/Config-abuild.lb
index 88dd1684e3..b1c927705b 100644
--- a/targets/amd/serengeti_cheetah/Config-abuild.lb
+++ b/targets/amd/serengeti_cheetah/Config-abuild.lb
@@ -4,33 +4,33 @@ target VENDOR_MAINBOARD
 mainboard VENDOR/MAINBOARD
 
 option CC="CROSSCC"
-option CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option CONFIG_HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 __LOGLEVEL__
 
 romimage "normal"
-	option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=0x20000
+	option CONFIG_USE_FAILOVER_IMAGE=0
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-normal"
 	payload __PAYLOAD__
 end
 
 romimage "fallback"
-	option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x20000
+	option CONFIG_USE_FAILOVER_IMAGE=0
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
 
 romimage "failover"
-	option USE_FAILOVER_IMAGE=1
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=FAILOVER_SIZE
-	option XIP_ROM_SIZE=FAILOVER_SIZE
+	option CONFIG_USE_FAILOVER_IMAGE=1
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 end
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
diff --git a/targets/amd/serengeti_cheetah/Config-lab.lb b/targets/amd/serengeti_cheetah/Config-lab.lb
index 42cefc190e..bcb443bcac 100644
--- a/targets/amd/serengeti_cheetah/Config-lab.lb
+++ b/targets/amd/serengeti_cheetah/Config-lab.lb
@@ -5,20 +5,20 @@
 target serengeti_cheetah
 mainboard amd/serengeti_cheetah
 
-option ROM_SIZE = 0x100000
-option USE_FAILOVER_IMAGE=0
-option HAVE_FAILOVER_BOOT=0
-option FAILOVER_SIZE=0
+option CONFIG_ROM_SIZE = 0x100000
+option CONFIG_USE_FAILOVER_IMAGE=0
+option CONFIG_HAVE_FAILOVER_BOOT=0
+option CONFIG_FAILOVER_SIZE=0
 
 romimage "fallback"
 	option CONFIG_PRECOMPRESSED_PAYLOAD=1
 	option CONFIG_COMPRESSED_PAYLOAD_LZMA=1
-	option FALLBACK_SIZE=ROM_SIZE
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x1a000
-	option XIP_ROM_SIZE=0x40000
+	option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x1a000
+	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 	payload ../payload.elf.lzma
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
diff --git a/targets/amd/serengeti_cheetah/Config.lb b/targets/amd/serengeti_cheetah/Config.lb
index a23505f6d3..ce180ea3d9 100644
--- a/targets/amd/serengeti_cheetah/Config.lb
+++ b/targets/amd/serengeti_cheetah/Config.lb
@@ -8,18 +8,18 @@ mainboard amd/serengeti_cheetah
 # serengeti_leopard
 romimage "normal"
 #       48K for SCSI FW
-#        option ROM_SIZE = 475136
+#        option CONFIG_ROM_SIZE = 475136
 #       48K for SCSI FW and 48K for ATI ROM
-#       option ROM_SIZE = 425984 
+#       option CONFIG_ROM_SIZE = 425984 
 #       64K for Etherboot
-#        option ROM_SIZE = 458752 
-	option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=0
-#	option ROM_IMAGE_SIZE=0x13800
-#	option ROM_IMAGE_SIZE=0x18800
-	option ROM_IMAGE_SIZE=0x20000
-#	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x40000
+#        option CONFIG_ROM_SIZE = 458752 
+	option CONFIG_USE_FAILOVER_IMAGE=0
+	option CONFIG_USE_FALLBACK_IMAGE=0
+#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_ROM_IMAGE_SIZE=0x18800
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #       payload ../../../payloads/tg3--ide_disk.zelf
 #        payload ../../../payloads/filo.elf
@@ -42,13 +42,13 @@ romimage "normal"
 end
 
 romimage "fallback" 
-	option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=1
-#	option ROM_IMAGE_SIZE=0x13800
-#	option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x20000
-#	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x40000
+	option CONFIG_USE_FAILOVER_IMAGE=0
+	option CONFIG_USE_FALLBACK_IMAGE=1
+#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_ROM_IMAGE_SIZE=0x19800
+	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 #       payload ../../../payloads/tg3--ide_disk.zelf
 #        payload ../../../payloads/filo.elf
@@ -75,13 +75,13 @@ romimage "fallback"
 end
 
 romimage "failover"
-	option USE_FAILOVER_IMAGE=1
-        option USE_FALLBACK_IMAGE=0
-        option ROM_IMAGE_SIZE=FAILOVER_SIZE
-        option XIP_ROM_SIZE=FAILOVER_SIZE
+	option CONFIG_USE_FAILOVER_IMAGE=1
+        option CONFIG_USE_FALLBACK_IMAGE=0
+        option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+        option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
         option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
 
-buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" 
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" 
diff --git a/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb b/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
index 996a1b50c3..6892a0eaa2 100644
--- a/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
+++ b/targets/amd/serengeti_cheetah_fam10/Config-abuild.lb
@@ -4,27 +4,27 @@ target VENDOR_MAINBOARD
 mainboard VENDOR/MAINBOARD
 
 option CC="CROSSCC"
-option CROSS_COMPILE="CROSS_PREFIX"
-option HOSTCC="CROSS_HOSTCC"
+option CONFIG_CROSS_COMPILE="CROSS_PREFIX"
+option CONFIG_HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 __LOGLEVEL__
 
-option ROM_SIZE=1024*1024
+option CONFIG_ROM_SIZE=1024*1024
 
 romimage "fallback" 
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x3f000
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x3f000
 	option COREBOOT_EXTRA_VERSION=".0-fallback"
 	payload __PAYLOAD__
 end
 
 romimage "failover"
-	option USE_FAILOVER_IMAGE=1
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=FAILOVER_SIZE
-	option XIP_ROM_SIZE=FAILOVER_SIZE
+	option CONFIG_USE_FAILOVER_IMAGE=1
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION=".0-failover"
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
diff --git a/targets/amd/serengeti_cheetah_fam10/Config-lab.lb b/targets/amd/serengeti_cheetah_fam10/Config-lab.lb
index 61e1b3c762..7cc594cd7d 100644
--- a/targets/amd/serengeti_cheetah_fam10/Config-lab.lb
+++ b/targets/amd/serengeti_cheetah_fam10/Config-lab.lb
@@ -25,30 +25,30 @@
 target serengeti_cheetah_fam10
 mainboard amd/serengeti_cheetah_fam10
 # Request this level of debugging output
-	option  DEFAULT_CONSOLE_LOGLEVEL=9
+	option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
 # At a maximum only compile in this level of debugging
-	option  MAXIMUM_CONSOLE_LOGLEVEL=9
+	option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 
 # 1024KB ROM
-option ROM_SIZE=1024*1024
-option FALLBACK_SIZE=ROM_SIZE-FAILOVER_SIZE
+option CONFIG_ROM_SIZE=1024*1024
+option CONFIG_FALLBACK_SIZE=CONFIG_ROM_SIZE-CONFIG_FAILOVER_SIZE
 
 romimage "fallback"
-	option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=1
-	option ROM_IMAGE_SIZE=0x30000
-	option XIP_ROM_SIZE=0x40000
+	option CONFIG_USE_FAILOVER_IMAGE=0
+	option CONFIG_USE_FALLBACK_IMAGE=1
+	option CONFIG_ROM_IMAGE_SIZE=0x30000
+	option CONFIG_XIP_ROM_SIZE=0x40000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf.lzma
 end
 
 romimage "failover"
-	option USE_FAILOVER_IMAGE=1
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=FAILOVER_SIZE
-	option XIP_ROM_SIZE=FAILOVER_SIZE
+	option CONFIG_USE_FAILOVER_IMAGE=1
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
-buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"
 
diff --git a/targets/amd/serengeti_cheetah_fam10/Config.lb b/targets/amd/serengeti_cheetah_fam10/Config.lb
index cad35150b6..189d536277 100644
--- a/targets/amd/serengeti_cheetah_fam10/Config.lb
+++ b/targets/amd/serengeti_cheetah_fam10/Config.lb
@@ -25,46 +25,46 @@
 target serengeti_cheetah_fam10
 mainboard amd/serengeti_cheetah_fam10
 # Request this level of debugging output
-	option  DEFAULT_CONSOLE_LOGLEVEL=9
+	option  CONFIG_DEFAULT_CONSOLE_LOGLEVEL=9
 # At a maximum only compile in this level of debugging
-	option  MAXIMUM_CONSOLE_LOGLEVEL=9
+	option  CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
 
 # 512KB ROM
-option ROM_SIZE=1024*1024
+option CONFIG_ROM_SIZE=1024*1024
 
 # Cheetah Family 10
 #romimage "normal"
 #	1MB ROM
-#	option ROM_SIZE = 0x100000
-#	option USE_FAILOVER_IMAGE=0
-#	option USE_FALLBACK_IMAGE=0
-#	option ROM_IMAGE_SIZE=0x20000
-#	option ROM_IMAGE_SIZE=0x30000
-#	option XIP_ROM_SIZE=0x40000
+#	option CONFIG_ROM_SIZE = 0x100000
+#	option CONFIG_USE_FAILOVER_IMAGE=0
+#	option CONFIG_USE_FALLBACK_IMAGE=0
+#	option CONFIG_ROM_IMAGE_SIZE=0x20000
+#	option CONFIG_ROM_IMAGE_SIZE=0x30000
+#	option CONFIG_XIP_ROM_SIZE=0x40000
 #	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
 #	payload ../payload.elf
 #end
 
 romimage "fallback"
-	option USE_FAILOVER_IMAGE=0
-	option USE_FALLBACK_IMAGE=1
-#	option ROM_IMAGE_SIZE=0x13800
-#	option ROM_IMAGE_SIZE=0x19800
-	option ROM_IMAGE_SIZE=0x7f000
-#	option ROM_IMAGE_SIZE=0x15800
-	option XIP_ROM_SIZE=0x80000
+	option CONFIG_USE_FAILOVER_IMAGE=0
+	option CONFIG_USE_FALLBACK_IMAGE=1
+#	option CONFIG_ROM_IMAGE_SIZE=0x13800
+#	option CONFIG_ROM_IMAGE_SIZE=0x19800
+	option CONFIG_ROM_IMAGE_SIZE=0x7f000
+#	option CONFIG_ROM_IMAGE_SIZE=0x15800
+	option CONFIG_XIP_ROM_SIZE=0x80000
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
 	payload ../payload.elf
 end
 
 romimage "failover"
-	option USE_FAILOVER_IMAGE=1
-	option USE_FALLBACK_IMAGE=0
-	option ROM_IMAGE_SIZE=FAILOVER_SIZE
-	option XIP_ROM_SIZE=FAILOVER_SIZE
+	option CONFIG_USE_FAILOVER_IMAGE=1
+	option CONFIG_USE_FALLBACK_IMAGE=0
+	option CONFIG_ROM_IMAGE_SIZE=CONFIG_FAILOVER_SIZE
+	option CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
 	option COREBOOT_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
 end
 
-#buildrom ./coreboot.rom ROM_SIZE "normal" "fallback" "failover"
-buildrom ./coreboot.rom ROM_SIZE "fallback" "failover"
+#buildrom ./coreboot.rom CONFIG_ROM_SIZE "normal" "fallback" "failover"
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback" "failover"