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authorStefan Reinauer <stepan@openbios.org>2003-09-11 11:55:18 +0000
committerStefan Reinauer <stepan@openbios.org>2003-09-11 11:55:18 +0000
commit1bb45d5a42285e369315e2ef4567deed4172f086 (patch)
tree35ca5dedb43c1288cac0b792bf764a47e08b9806 /targets/amd
parent79249e3dbc955c255b1b53107b3a5488775f5690 (diff)
add quartet and dspace targets, disable reboot in Solo target.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1110 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'targets/amd')
-rw-r--r--targets/amd/quartet/Config.lb106
-rw-r--r--targets/amd/solo/Config.lb2
2 files changed, 107 insertions, 1 deletions
diff --git a/targets/amd/quartet/Config.lb b/targets/amd/quartet/Config.lb
new file mode 100644
index 0000000000..6fc5ea0c8d
--- /dev/null
+++ b/targets/amd/quartet/Config.lb
@@ -0,0 +1,106 @@
+# Sample config file for building AMD Quartet images
+# This will make a target directory of ./quartet
+
+loadoptions
+
+target quartet
+
+uses ARCH
+uses CONFIG_COMPRESS
+uses CONFIG_IOAPIC
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_UDELAY_TSC
+uses CPU_FIXUP
+uses FALLBACK_SIZE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_HARD_RESET
+uses i586
+uses i686
+uses INTEL_PPRO_MTRR
+uses HEAP_SIZE
+uses IRQ_SLOT_COUNT
+uses k7
+uses k8
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses CONFIG_SMP
+uses CONFIG_MAX_CPUS
+uses MEMORY_HOLE
+uses PAYLOAD_SIZE
+uses _RAMBASE
+uses _ROMBASE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_OFFSET
+uses ROM_SECTION_SIZE
+uses ROM_SIZE
+uses STACK_SIZE
+uses USE_FALLBACK_IMAGE
+uses USE_OPTION_TABLE
+uses HAVE_OPTION_TABLE
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_SERIAL8250
+uses MAINBOARD
+uses CONFIG_CHIP_CONFIGURE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses LINUXBIOS_EXTRA_VERSION
+
+option CONFIG_CHIP_CONFIGURE=1
+
+option MAXIMUM_CONSOLE_LOGLEVEL=7
+option DEFAULT_CONSOLE_LOGLEVEL=7
+option CONFIG_CONSOLE_SERIAL8250=1
+
+option CPU_FIXUP=1
+option CONFIG_UDELAY_TSC=0
+option i686=1
+option i586=1
+option INTEL_PPRO_MTRR=1
+option k7=1
+option k8=1
+
+option ROM_SIZE=524288
+
+
+option HAVE_OPTION_TABLE=1
+option CONFIG_ROM_STREAM=1
+option HAVE_FALLBACK_BOOT=1
+
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+option FALLBACK_SIZE=0x40000
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+
+#
+# AMD Quartet
+romimage "normal"
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION=".0Normal"
+ mainboard amd/quartet
+ payload /suse/stepan/tg3--ide_disk.zelf
+end
+
+romimage "fallback"
+ option USE_FALLBACK_IMAGE=1
+ option ROM_IMAGE_SIZE=0x10000
+ option LINUXBIOS_EXTRA_VERSION=".0Fallback"
+ mainboard amd/quartet
+ payload /suse/stepan/tg3--ide_disk.zelf
+end
+
+buildrom ROM_SIZE "normal" "fallback"
diff --git a/targets/amd/solo/Config.lb b/targets/amd/solo/Config.lb
index 2955720e21..9f34258e75 100644
--- a/targets/amd/solo/Config.lb
+++ b/targets/amd/solo/Config.lb
@@ -86,7 +86,7 @@ option _RAMBASE=0x00004000
###
#
-# Arima hdama
+# AMD Solo
romimage "normal"
option USE_FALLBACK_IMAGE=0
option ROM_IMAGE_SIZE=0x10000