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authorElyes Haouas <ehaouas@noos.fr>2022-02-20 11:09:07 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-22 17:40:30 +0000
commitfd93cff32928bff8d6ca52ed8536fcffa37f0e68 (patch)
tree161d0493631e99e22ae18bf309bba7afb6774b2a /src
parent7f7ac206f8b555c92cc8e3181ce24ca1348a04c4 (diff)
treewide: Get rid of CONFIG_AZALIA_MAX_CODECS
Get rid of Kconfig symbol introduced at commit 5d31dfa8 High Definition Audio Specification Revision 1.0a says, there are 15 SDIWAKE bits. Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Change-Id: Ib8b656daca52e21cb0c7120b208a2acdd88625e1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/62202 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/device/Kconfig8
-rw-r--r--src/device/azalia_device.c11
-rw-r--r--src/soc/intel/broadwell/pch/Kconfig3
-rw-r--r--src/soc/intel/common/block/hda/Kconfig3
-rw-r--r--src/southbridge/intel/bd82x6x/Kconfig3
-rw-r--r--src/southbridge/intel/i82801gx/Kconfig3
-rw-r--r--src/southbridge/intel/i82801ix/Kconfig3
-rw-r--r--src/southbridge/intel/i82801jx/Kconfig3
-rw-r--r--src/southbridge/intel/ibexpeak/Kconfig3
-rw-r--r--src/southbridge/intel/lynxpoint/Kconfig3
10 files changed, 5 insertions, 38 deletions
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 8471d5d00e..7f20d709ad 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -527,14 +527,6 @@ config AZALIA_PLUGIN_SUPPORT
bool
default n
-config AZALIA_MAX_CODECS
- int
- depends on AZALIA_PLUGIN_SUPPORT
- default 3
- range 1 15
- help
- The maximum number of codecs supported on a single HD Audio controller.
-
config AZALIA_LOCK_DOWN_R_WO_GCAP
def_bool n
depends on AZALIA_PLUGIN_SUPPORT
diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c
index e61e1dcd77..4ac585dac1 100644
--- a/src/device/azalia_device.c
+++ b/src/device/azalia_device.c
@@ -50,7 +50,6 @@ int azalia_exit_reset(u8 *base)
static u16 codec_detect(u8 *base)
{
struct stopwatch sw;
- const u16 codec_mask = (1 << CONFIG_AZALIA_MAX_CODECS) - 1;
u16 reg16;
if (azalia_exit_reset(base) < 0)
@@ -61,9 +60,9 @@ static u16 codec_detect(u8 *base)
write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG));
}
- /* clear STATESTS bits (BAR + 0xe)[2:0] */
+ /* clear STATESTS bits (BAR + 0x0e)[14:0] */
reg16 = read16(base + HDA_STATESTS_REG);
- reg16 |= codec_mask;
+ reg16 |= 0x7fff;
write16(base + HDA_STATESTS_REG, reg16);
/* Wait for readback of register to
@@ -86,9 +85,9 @@ static u16 codec_detect(u8 *base)
if (azalia_exit_reset(base) < 0)
goto no_codec;
- /* Read in Codec location (BAR + 0xe)[2..0] */
+ /* Read in Codec location (BAR + 0x0e)[14:0] */
reg16 = read16(base + HDA_STATESTS_REG);
- reg16 &= codec_mask;
+ reg16 &= 0x7fff;
if (!reg16)
goto no_codec;
@@ -274,7 +273,7 @@ void azalia_codecs_init(u8 *base, u16 codec_mask)
{
int i;
- for (i = CONFIG_AZALIA_MAX_CODECS - 1; i >= 0; i--) {
+ for (i = 14; i >= 0; i--) {
if (codec_mask & (1 << i))
azalia_codec_init(base, i, cim_verb_data, cim_verb_data_size);
}
diff --git a/src/soc/intel/broadwell/pch/Kconfig b/src/soc/intel/broadwell/pch/Kconfig
index 3fbaa79bc2..4e187ff114 100644
--- a/src/soc/intel/broadwell/pch/Kconfig
+++ b/src/soc/intel/broadwell/pch/Kconfig
@@ -24,9 +24,6 @@ config PCH_SPECIFIC_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9
select SPI_FLASH
-config AZALIA_MAX_CODECS
- default 4
-
config EHCI_BAR
hex
default 0xd8000000
diff --git a/src/soc/intel/common/block/hda/Kconfig b/src/soc/intel/common/block/hda/Kconfig
index a01ede4ac6..193e1fcb8d 100644
--- a/src/soc/intel/common/block/hda/Kconfig
+++ b/src/soc/intel/common/block/hda/Kconfig
@@ -9,6 +9,3 @@ config SOC_INTEL_COMMON_BLOCK_HDA_VERB
select AZALIA_LOCK_DOWN_R_WO_GCAP
help
Enable initialization of HDA codecs.
-
-config AZALIA_MAX_CODECS
- default 4 if SOC_INTEL_COMMON_BLOCK_HDA_VERB
diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig
index ee8a5ccc56..c9e86625d2 100644
--- a/src/southbridge/intel/bd82x6x/Kconfig
+++ b/src/southbridge/intel/bd82x6x/Kconfig
@@ -37,9 +37,6 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
-config AZALIA_MAX_CODECS
- default 4
-
config EHCI_BAR
hex
default 0xfef00000
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index feaf081256..399d7e0bbb 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -25,9 +25,6 @@ config SOUTHBRIDGE_INTEL_I82801GX
if SOUTHBRIDGE_INTEL_I82801GX
-config AZALIA_MAX_CODECS
- default 3
-
config EHCI_BAR
hex
default 0xfef00000
diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index 879d525bd0..39f5e83b25 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -24,9 +24,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
if SOUTHBRIDGE_INTEL_I82801IX
-config AZALIA_MAX_CODECS
- default 4
-
config EHCI_BAR
hex
default 0xfef00000
diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig
index 6cd90e053e..197ed523f6 100644
--- a/src/southbridge/intel/i82801jx/Kconfig
+++ b/src/southbridge/intel/i82801jx/Kconfig
@@ -25,9 +25,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
if SOUTHBRIDGE_INTEL_I82801JX
-config AZALIA_MAX_CODECS
- default 4
-
config EHCI_BAR
hex
default 0xfef00000
diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig
index b74cb7350d..6972da7613 100644
--- a/src/southbridge/intel/ibexpeak/Kconfig
+++ b/src/southbridge/intel/ibexpeak/Kconfig
@@ -33,9 +33,6 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_WATCHDOG
select SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG
-config AZALIA_MAX_CODECS
- default 4
-
config EHCI_BAR
hex
default 0xfef00000
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index b7c719be45..891b06a4a5 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -41,9 +41,6 @@ config INTEL_LYNXPOINT_LP
help
Set this option to y for LynxPoint LP (Haswell ULT).
-config AZALIA_MAX_CODECS
- default 4
-
config EHCI_BAR
hex
default 0xe8000000