diff options
| author | Leo Chou <leo.chou@lcfc.corp-partner.google.com> | 2022-07-22 15:55:59 +0800 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2022-07-27 13:37:23 +0000 |
| commit | f92ea61e84184610053f16a734319096f8fb6401 (patch) | |
| tree | 0b402fe823ce69bec27d5e5747b048f5a714ff93 /src | |
| parent | 7127013f7c93481c6823de84bd41f00188e64bab (diff) | |
mb/google/nissa/var/pujjo: Enable PCIe port 4 for WLAN
Pujjo support WLAN device, enable PCIe port 4 for WLAN device
BUG=b:239899932
TEST=Build and boot on pujjo
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Ic8b7240941cf87a4f27963d50fffe28875114a81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66073
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/brya/variants/pujjo/overridetree.cb | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/pujjo/overridetree.cb b/src/mainboard/google/brya/variants/pujjo/overridetree.cb index 647bcbfc30..5c4709f2d9 100644 --- a/src/mainboard/google/brya/variants/pujjo/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjo/overridetree.cb @@ -13,6 +13,7 @@ chip soc/intel/alderlake register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}" register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # WFC Camera + register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for PCIe WLAN register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth port for CNVi WLAN # Configure external V1P05/Vnn/VnnSx Rails @@ -228,6 +229,18 @@ chip soc/intel/alderlake device i2c 0x2c on end end end + device ref pcie_rp4 on + # PCIe 4 WLAN + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW1_03" + device pci 00.0 on end + end + end device ref pcie_rp7 on # Enable SD Card PCIe 7 using clk 3 register "pch_pcie_rp[PCH_RP(7)]" = "{ @@ -316,6 +329,13 @@ chip soc/intel/alderlake register "type" = "UPC_TYPE_INTERNAL" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""CNVi Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" device ref usb2_port10 on end end chip drivers/usb/acpi |