diff options
| author | Mario Scheithauer <mario.scheithauer@siemens.com> | 2023-05-10 14:25:24 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-05-24 11:25:24 +0000 |
| commit | f5a48989b4d005158917b9890340f416dad506f1 (patch) | |
| tree | 2a16b37f5d2f087e819caeea7fcf5e0176837f93 /src | |
| parent | a6d337badf0dbc6e56c9debc3062ce7f85ce863b (diff) | |
soc/intel/elkhartlake: Make PCIe root port max payload size configurable
The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.
This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.
Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/elkhartlake/chip.h | 6 | ||||
| -rw-r--r-- | src/soc/intel/elkhartlake/fsp_params.c | 1 |
2 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/chip.h b/src/soc/intel/elkhartlake/chip.h index 492a401eea..204d073365 100644 --- a/src/soc/intel/elkhartlake/chip.h +++ b/src/soc/intel/elkhartlake/chip.h @@ -240,6 +240,12 @@ struct soc_intel_elkhartlake_config { /* PCIe RP L1 substate */ enum L1_substates_control PcieRpL1Substates[CONFIG_MAX_ROOT_PORTS]; + /* PCIe root port maximum payload size, default is set to 128 bytes. */ + enum { + RpMaxPayload_128, + RpMaxPayload_256, + } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; + /* PCIe root port speed. 0: Auto (Default); 1: Gen1; 2: Gen2; 3: Gen3 */ uint8_t PcieRpPcieSpeed[CONFIG_MAX_ROOT_PORTS]; diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index a3213b151c..5e1bba78ea 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -388,6 +388,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PcieRpVc1TcMap[i] = 0x60; if (config->realtime_tuning_enable) params->PcieRpEnableCpm[i] = 0; + params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; } /* SATA config */ |