diff options
| author | Vaibhav Shankar <vaibhav.shankar@intel.com> | 2017-10-16 10:16:27 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-10-18 20:07:45 +0000 |
| commit | f36ed21c573d62583ca2a86eed594acd149e0c4c (patch) | |
| tree | a9c0f2a618b8343f6250a4fb217f6e8031120893 /src | |
| parent | f46a9a0d3ad3157de3e354b4314fe9c5c3b69dd2 (diff) | |
mainboard/intel/cannonlake_rvp: Enable hardware P state control
This patch provides configuration parameter to enable/disable
Intel Speed Shift Technology.
Change-Id: I95a240e8be6e19ac0e14698ab33543c491a8c974
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index b80cd82d50..c3223b1913 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -67,6 +67,9 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 9a0ab64672..4bada02fc8 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -65,6 +65,9 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device |