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authorCaveh Jalali <caveh@chromium.org>2018-08-08 16:59:12 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-08-15 09:36:55 +0000
commited365412b2856c1537d4172b1ebdd2e77010840a (patch)
treea6889578375353e38612869cba2176ed095a9eb9 /src
parentec6d01579b62b2b62947f501efd65fbafefcdb92 (diff)
mb/google/atlas: Update DPTF sensor names
This updates the DPTF sensor names to reflect the sensor locations on the board. BUG=b:75454415 TEST=verified new strings show up in /sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28069 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl
index bb42351279..685f4ddd36 100644
--- a/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl
+++ b/src/mainboard/google/poppy/variants/atlas/include/variant/acpi/dptf.asl
@@ -18,22 +18,22 @@
#define DPTF_CPU_CRITICAL 105
#define DPTF_TSR0_SENSOR_ID 1
-#define DPTF_TSR0_SENSOR_NAME "systherm0"
+#define DPTF_TSR0_SENSOR_NAME "Ambient"
#define DPTF_TSR0_PASSIVE 48
#define DPTF_TSR0_CRITICAL 90
#define DPTF_TSR1_SENSOR_ID 2
-#define DPTF_TSR1_SENSOR_NAME "systherm1"
+#define DPTF_TSR1_SENSOR_NAME "Charger"
#define DPTF_TSR1_PASSIVE 48
#define DPTF_TSR1_CRITICAL 90
#define DPTF_TSR2_SENSOR_ID 3
-#define DPTF_TSR2_SENSOR_NAME "systherm2"
+#define DPTF_TSR2_SENSOR_NAME "DRAM"
#define DPTF_TSR2_PASSIVE 65
#define DPTF_TSR2_CRITICAL 75
#define DPTF_TSR3_SENSOR_ID 4
-#define DPTF_TSR3_SENSOR_NAME "systherm3"
+#define DPTF_TSR3_SENSOR_NAME "eMMC"
#define DPTF_TSR3_PASSIVE 65
#define DPTF_TSR3_CRITICAL 75