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authorElyes HAOUAS <ehaouas@noos.fr>2018-07-03 18:34:10 +0200
committerPatrick Georgi <pgeorgi@google.com>2018-07-06 12:59:05 +0000
commitece7d0cfeaab2a61e10690bcf31d71cef3393749 (patch)
treeda424a7198fe70da6a87c2b8f0f680efe7e4b063 /src
parent145ef87b32324403d8a8372414d1d544527c129c (diff)
mb/ibase/mb899: Remove unneeded includes
Change-Id: Iee237206f309409be64307d2daee044da52a05e1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/ibase/mb899/mainboard.c7
-rw-r--r--src/mainboard/ibase/mb899/romstage.c19
2 files changed, 7 insertions, 19 deletions
diff --git a/src/mainboard/ibase/mb899/mainboard.c b/src/mainboard/ibase/mb899/mainboard.c
index 0629d3323b..d4d05c31dc 100644
--- a/src/mainboard/ibase/mb899/mainboard.c
+++ b/src/mainboard/ibase/mb899/mainboard.c
@@ -13,17 +13,10 @@
* GNU General Public License for more details.
*/
-#include <types.h>
#include <device/device.h>
-#include <console/console.h>
#include <drivers/intel/gma/int15.h>
-#include <pc80/mc146818rtc.h>
-#include <arch/io.h>
-#include <arch/interrupt.h>
#include "superio_hwm.h"
-
-
// mainboard_enable is executed as first thing after
// enumerate_buses().
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index dd384acc3a..78ec5ed200 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -16,25 +16,20 @@
// __PRE_RAM__ means: use "unsigned" for device, not a struct.
#include <stdint.h>
-#include <string.h>
+#include <halt.h>
#include <arch/io.h>
-#include <device/pci_def.h>
-#include <device/pnp_def.h>
-#include <cpu/x86/lapic.h>
-#include <lib.h>
-#include <arch/acpi.h>
-#include <cbmem.h>
#include <timestamp.h>
-#include <superio/winbond/common/winbond.h>
-#include <superio/winbond/w83627ehg/w83627ehg.h>
-#include <pc80/mc146818rtc.h>
#include <console/console.h>
-#include <cpu/x86/bist.h>
#include <cpu/intel/romstage.h>
-#include <halt.h>
+#include <cpu/x86/bist.h>
+#include <cpu/x86/lapic.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
#include <northbridge/intel/i945/i945.h>
#include <northbridge/intel/i945/raminit.h>
#include <southbridge/intel/i82801gx/i82801gx.h>
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627ehg/w83627ehg.h>
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
#define SUPERIO_DEV PNP_DEV(0x4e, 0)