soc/intel/meteorlake: Provide access to IOE through P2SB SBI for TCSS

This change provides access to IOE through P2SB Sideband interface for
Meteor Lake TCSS functions of pad configuration and Thunderbolt
authentication. There is a policy of locking the P2SB access at the end
of platform initialization. The tbt_authentication is read from IOM
register through IOE P2SB at early silicon initialization phase and its
usage is deferred to usb4 driver.

BUG=b:213574324
TEST=Built coreboot and validated booting to OS successfully on MTLRVP
board. No boot hung was observed.

Change-Id: Icd644c945bd293a8b9c4a364aaed99ec4a7c12f9
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

4 files changed, 22 insertions, 4 deletions

diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c
index 5b62c069da..f6e1d24725 100644
--- a/src/soc/intel/meteorlake/chip.c
+++ b/src/soc/intel/meteorlake/chip.c
@@ -8,16 +8,20 @@
 #include <intelblocks/cfg.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/itss.h>
+#include <intelblocks/p2sb.h>
 #include <intelblocks/pcie_rp.h>
 #include <intelblocks/systemagent.h>
+#include <intelblocks/tcss.h>
 #include <intelblocks/xdci.h>
 #include <soc/intel/common/vbt.h>
+#include <soc/iomap.h>
 #include <soc/itss.h>
 #include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/pcie.h>
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
+#include <soc/tcss.h>
 
 #if CONFIG(HAVE_ACPI_TABLES)
 const char *soc_acpi_name(const struct device *dev)
@@ -129,6 +133,12 @@ static void soc_fill_gpio_pm_configuration(void)
 
 void soc_init_pre_device(void *chip_info)
 {
+	config_t *config = config_of_soc();
+
+	/* Validate TBT image authentication */
+	config->tbt_authentication = ioe_p2sb_sbi_read(PID_IOM,
+					IOM_CSME_IMR_TBT_STATUS) & TBT_VALID_AUTHENTICATION;
+
 	/* Perform silicon specific init. */
 	fsp_silicon_init();
 
diff --git a/src/soc/intel/meteorlake/chip.h b/src/soc/intel/meteorlake/chip.h
index 05d77f3d1c..04b8299b2d 100644
--- a/src/soc/intel/meteorlake/chip.h
+++ b/src/soc/intel/meteorlake/chip.h
@@ -126,6 +126,8 @@ struct soc_intel_meteorlake_config {
 	/* Program OC pins for TCSS */
 	struct tcss_port_config tcss_ports[MAX_TYPE_C_PORTS];
 	uint8_t tbt_pcie_port_disable[4];
+	/* Validate TBT firmware authenticated and loaded into IMR */
+	bool tbt_authentication;
 
 	/* SATA related */
 	uint8_t sata_mode;
diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c
index 3ca6c52da6..ff17a35a36 100644
--- a/src/soc/intel/meteorlake/fsp_params.c
+++ b/src/soc/intel/meteorlake/fsp_params.c
@@ -14,8 +14,8 @@
 #include <intelblocks/lpss.h>
 #include <intelblocks/xdci.h>
 #include <intelpch/lockdown.h>
-#include <intelblocks/tcss.h>
 #include <security/vboot/vboot_common.h>
+#include <soc/cpu.h>
 #include <soc/gpio_soc_defs.h>
 #include <soc/intel/common/vbt.h>
 #include <soc/pci_devs.h>
@@ -23,7 +23,6 @@
 #include <soc/ramstage.h>
 #include <soc/soc_chip.h>
 #include <soc/soc_info.h>
-#include <soc/cpu.h>
 #include <string.h>
 
 /* THC assignment definition */
diff --git a/src/soc/intel/meteorlake/tcss.c b/src/soc/intel/meteorlake/tcss.c
index c51fe6c41f..7509504eea 100644
--- a/src/soc/intel/meteorlake/tcss.c
+++ b/src/soc/intel/meteorlake/tcss.c
@@ -1,8 +1,15 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <intelblocks/tcss.h>
+#include <soc/soc_chip.h>
 
 const struct soc_tcss_ops tcss_ops = {
-	.configure_aux_bias_pads = tcss_configure_aux_bias_pads_regbar,
-	.valid_tbt_auth = tcss_valid_tbt_auth,
+	.configure_aux_bias_pads = ioe_tcss_configure_aux_bias_pads_sbi,
+	.valid_tbt_auth = ioe_tcss_valid_tbt_auth,
 };
+
+bool ioe_tcss_valid_tbt_auth(void)
+{
+	const config_t *config = config_of_soc();
+	return config->tbt_authentication;
+}