diff options
| author | Uwe Poeche <uwe.poeche@siemens.com> | 2022-04-04 15:10:28 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-04-06 16:20:27 +0000 |
| commit | e9b417c0a0fed113e4254510513f847ec56b5bb3 (patch) | |
| tree | f5a35f2323c9b7fc5c0da8179d1b0350814396c0 /src | |
| parent | ca74d7e65b9562e4d84079af3583524d9e82460f (diff) | |
soc/intel/ehl/fsp_params: Set Intel Speed Step (Eist) from devicetree
This patch provides the set value for intel speed step in devicetree
for FSPS. Before that in case of not set value in device tree the
default value of disabled was overwritten by default enabled of FSP.
Test: mainboard/siemens/mc_ehl/variants/mc_ehl1
Check status of Bit 16 in MSR 0x1a0 after boot.
Change-Id: I0a5ef4968a27978116c21ce35b3818c6b36e086f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/elkhartlake/fsp_params.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 1584c6af6c..2100cc4ded 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -264,6 +264,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->DdiPortCHpd = config->DdiPortCHpd; params->DdiPortCDdc = config->DdiPortCDdc; + /* Intel Speed Step */ + params->Eist = config->eist_enable; + /* Use coreboot MP PPI services if Kconfig is enabled */ if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |