mb/google/glados: drop VR configs from devicetree

The VR config values used in the variants' devicetrees is
identical to the domain defaults in vr_config.c, with the
exception of the icc_max value, which is calculated dynamically
based on SKU, and again matches the default values for
each domain and each varaint.

Test: add a print function to dump the VR config values for each
domain from the UPDs after setting, verify same output before/after.

Change-Id: I4307f6e19ae6f99d4f5e475b181fd66c5b92f28c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39982
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

7 files changed, 0 insertions, 469 deletions

diff --git a/src/mainboard/google/glados/variants/asuka/devicetree.cb b/src/mainboard/google/glados/variants/asuka/devicetree.cb
index e1e68caff7..395b5728b7 100644
--- a/src/mainboard/google/glados/variants/asuka/devicetree.cb
+++ b/src/mainboard/google/glados/variants/asuka/devicetree.cb
@@ -70,72 +70,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 4 Domains
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
-	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
-	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
-	#| Psi3Enable     | 1         | 1         | 1           | 1        |
-	#| Psi4Enable     | 1         | 1         | 1           | 1        |
-	#| ImonSlope      | 0         | 0         | 0           | 0        |
-	#| ImonOffset     | 0         | 0         | 0           | 0        |
-	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
-	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
-	#+----------------+-----------+-----------+-------------+----------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(4),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(7),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
 	# Enable CLKREQ#
diff --git a/src/mainboard/google/glados/variants/caroline/devicetree.cb b/src/mainboard/google/glados/variants/caroline/devicetree.cb
index 00b29b7699..3e733d6b1c 100644
--- a/src/mainboard/google/glados/variants/caroline/devicetree.cb
+++ b/src/mainboard/google/glados/variants/caroline/devicetree.cb
@@ -77,72 +77,6 @@ chip soc/intel/skylake
 	register "SlowSlewRateForSa" = "0"	# Fast/2
 	register "FastPkgCRampDisable" = "0"
 
-	# VR Settings Configuration for 4 Domains
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
-	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
-	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
-	#| Psi3Enable     | 1         | 1         | 1           | 1        |
-	#| Psi4Enable     | 1         | 1         | 1           | 1        |
-	#| ImonSlope      | 0         | 0         | 0           | 0        |
-	#| ImonOffset     | 0         | 0         | 0           | 0        |
-	#| IccMax         | 4A        | 24A       | 24A         | 24A      |
-	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
-	#+----------------+-----------+-----------+-------------+----------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(4),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(4),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
 	# Enable CLKREQ#
diff --git a/src/mainboard/google/glados/variants/cave/devicetree.cb b/src/mainboard/google/glados/variants/cave/devicetree.cb
index 41bb82e053..ccc2302a58 100644
--- a/src/mainboard/google/glados/variants/cave/devicetree.cb
+++ b/src/mainboard/google/glados/variants/cave/devicetree.cb
@@ -70,72 +70,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 4 Domains
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
-	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
-	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
-	#| Psi3Enable     | 1         | 1         | 1           | 1        |
-	#| Psi4Enable     | 1         | 1         | 1           | 1        |
-	#| ImonSlope      | 0         | 0         | 0           | 0        |
-	#| ImonOffset     | 0         | 0         | 0           | 0        |
-	#| IccMax         | 4A        | 24A       | 24A         | 24A      |
-	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
-	#+----------------+-----------+-----------+-------------+----------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(4),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(4),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
 	# Enable CLKREQ#
diff --git a/src/mainboard/google/glados/variants/chell/devicetree.cb b/src/mainboard/google/glados/variants/chell/devicetree.cb
index c0fb07c7ef..bbc74f8d97 100644
--- a/src/mainboard/google/glados/variants/chell/devicetree.cb
+++ b/src/mainboard/google/glados/variants/chell/devicetree.cb
@@ -70,72 +70,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 4 Domains
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
-	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
-	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
-	#| Psi3Enable     | 1         | 1         | 1           | 1        |
-	#| Psi4Enable     | 1         | 1         | 1           | 1        |
-	#| ImonSlope      | 0         | 0         | 0           | 0        |
-	#| ImonOffset     | 0         | 0         | 0           | 0        |
-	#| IccMax         | 4A        | 24A       | 24A         | 24A      |
-	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
-	#+----------------+-----------+-----------+-------------+----------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(4),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(4),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(24),
-		.voltage_limit = 1520,
-	}"
-
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
 	# Enable CLKREQ#
diff --git a/src/mainboard/google/glados/variants/glados/devicetree.cb b/src/mainboard/google/glados/variants/glados/devicetree.cb
index d63d9c12e5..9cd5ac986f 100644
--- a/src/mainboard/google/glados/variants/glados/devicetree.cb
+++ b/src/mainboard/google/glados/variants/glados/devicetree.cb
@@ -70,72 +70,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 4 Domains
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
-	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
-	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
-	#| Psi3Enable     | 1         | 1         | 1           | 1        |
-	#| Psi4Enable     | 1         | 1         | 1           | 1        |
-	#| ImonSlope      | 0         | 0         | 0           | 0        |
-	#| ImonOffset     | 0         | 0         | 0           | 0        |
-	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
-	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
-	#+----------------+-----------+-----------+-------------+----------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(4),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(7),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
 	# Enable CLKREQ#
diff --git a/src/mainboard/google/glados/variants/lars/devicetree.cb b/src/mainboard/google/glados/variants/lars/devicetree.cb
index 419d14026c..35ce9a0294 100644
--- a/src/mainboard/google/glados/variants/lars/devicetree.cb
+++ b/src/mainboard/google/glados/variants/lars/devicetree.cb
@@ -70,72 +70,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 4 Domains
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
-	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
-	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
-	#| Psi3Enable     | 1         | 1         | 1           | 1        |
-	#| Psi4Enable     | 1         | 1         | 1           | 1        |
-	#| ImonSlope      | 0         | 0         | 0           | 0        |
-	#| ImonOffset     | 0         | 0         | 0           | 0        |
-	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
-	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
-	#+----------------+-----------+-----------+-------------+----------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(4),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(7),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
 	# Enable CLKREQ#
diff --git a/src/mainboard/google/glados/variants/sentry/devicetree.cb b/src/mainboard/google/glados/variants/sentry/devicetree.cb
index 57586fb38e..502aad04ea 100644
--- a/src/mainboard/google/glados/variants/sentry/devicetree.cb
+++ b/src/mainboard/google/glados/variants/sentry/devicetree.cb
@@ -70,72 +70,6 @@ chip soc/intel/skylake
 	register "pirqg_routing" = "PCH_IRQ11"
 	register "pirqh_routing" = "PCH_IRQ11"
 
-	# VR Settings Configuration for 4 Domains
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Domain/Setting |     SA    |    IA     | GT Unsliced |    GT    |
-	#+----------------+-----------+-----------+-------------+----------+
-	#| Psi1Threshold  | 20A       | 20A       | 20A         | 20A      |
-	#| Psi2Threshold  | 4A        | 5A        | 5A          | 5A       |
-	#| Psi3Threshold  | 1A        | 1A        | 1A          | 1A       |
-	#| Psi3Enable     | 1         | 1         | 1           | 1        |
-	#| Psi4Enable     | 1         | 1         | 1           | 1        |
-	#| ImonSlope      | 0         | 0         | 0           | 0        |
-	#| ImonOffset     | 0         | 0         | 0           | 0        |
-	#| IccMax         | 7A        | 34A       | 35A         | 35A      |
-	#| VrVoltageLimit | 1.52V     | 1.52V     | 1.52V       | 1.52V    |
-	#+----------------+-----------+-----------+-------------+----------+
-	register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(4),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(7),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_IA_CORE]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(34),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_UNSLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
-	register "domain_vr_config[VR_GT_SLICED]" = "{
-		.vr_config_enable = 1,
-		.psi1threshold = VR_CFG_AMP(20),
-		.psi2threshold = VR_CFG_AMP(5),
-		.psi3threshold = VR_CFG_AMP(1),
-		.psi3enable = 1,
-		.psi4enable = 1,
-		.imon_slope = 0x0,
-		.imon_offset = 0x0,
-		.icc_max = VR_CFG_AMP(35),
-		.voltage_limit = 1520,
-	}"
-
 	# Enable Root port 1
 	register "PcieRpEnable[0]" = "1"
 	# Enable CLKREQ#
@@ -143,13 +77,6 @@ chip soc/intel/skylake
 	# RP 1 uses SRCCLKREQ1#
 	register "PcieRpClkReqNumber[0]" = "1"
 
-	# Enable Root port 5
-	register "PcieRpEnable[4]" = "1"
-	# Enable CLKREQ#
-	register "PcieRpClkReqSupport[4]" = "1"
-	# RP 5 uses SRCCLKREQ2#
-	register "PcieRpClkReqNumber[4]" = "2"
-
 	register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"	# Type-C Port 1
 	register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC1)"	# Type-C Port 2
 	register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)"	# Bluetooth