diff options
| author | Felix Held <felix-coreboot@felixheld.de> | 2023-01-19 17:04:47 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-01-23 19:14:24 +0000 |
| commit | e3adefedca3d35a576c87ff8584dacc61f5587b1 (patch) | |
| tree | 27eb4b933501bf2e45da80f4edc9ffd4c85a5a7d /src | |
| parent | 141a1772cac7be67fd007377f567a8b356d5c6c1 (diff) | |
soc/amd/mendocino/acpi: remove RTC wake workaround
Commit 78ee4889dc32 ("soc/amd/cezanne/acpi: Add support for RTC
workaround") added a workaround for the Cezanne silicon. This was copied
to the Mendocino code, but from both the discussion in b:209705576 and
the referenced amd_pmc_verify_czn_rtc function in drivers/platform/x86/
amd/pmc.c that is only called if pdev->cpu_id == AMD_CPU_ID_CZN is true
Mendocino doesn't need that workaround, so remove it.
TEST=Running suspend_stress_test -c 5 on Chausie shows no errors
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7d0b35ef8cf88ff0b9bed8820b8da32c2058cc1b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72091
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/amd/mendocino/acpi/rtc_workaround.asl | 28 | ||||
| -rw-r--r-- | src/soc/amd/mendocino/acpi/soc.asl | 2 |
2 files changed, 0 insertions, 30 deletions
diff --git a/src/soc/amd/mendocino/acpi/rtc_workaround.asl b/src/soc/amd/mendocino/acpi/rtc_workaround.asl deleted file mode 100644 index 8bbca4e3f1..0000000000 --- a/src/soc/amd/mendocino/acpi/rtc_workaround.asl +++ /dev/null @@ -1,28 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* TODO: Check if this is still correct */ - -/* - * Workaround for RTC on Cezanne. - * See https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.10/drivers/platform/x86/amd-pmc.c;l=416;drc=54a96af06ae6851e4a02e8dd700de0d579ef7839 - */ - -Scope (\_SB.PEP) { - Name (_PRW, Package () { - Package() {\_SB.GPIO, 0}, - 0x03 - }) -} - -Scope (\_SB.GPIO) { - Name (_AEI, ResourceTemplate () { - GpioInt(Edge, ActiveHigh, ExclusiveAndWake, PullNone, 0x0000, "\\_SB.GPIO",,,,) - { - 44 /* int_shdwsysalarmfire */ - } - }) - - Method (_E2C, 0, Serialized) { - Notify (\_SB_.PEP, 0x02) - } -} diff --git a/src/soc/amd/mendocino/acpi/soc.asl b/src/soc/amd/mendocino/acpi/soc.asl index 5af6d8c533..7e9e2e8cc2 100644 --- a/src/soc/amd/mendocino/acpi/soc.asl +++ b/src/soc/amd/mendocino/acpi/soc.asl @@ -33,8 +33,6 @@ Scope(\_SB) { #include <soc/amd/common/acpi/dptc.asl> #endif -#include "rtc_workaround.asl" - /* Enable DPTC interface with AMD ALIB */ External(\_SB.DPTC, MethodObj) |