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| author | Kane Chen <kane.chen@intel.com> | 2014-07-17 11:31:57 -0700 |
|---|---|---|
| committer | Marc Jones <marc.jones@se-eng.com> | 2015-01-16 20:50:32 +0100 |
| commit | e3815442925619af88617ab572dff622a42810d1 (patch) | |
| tree | c6b63065c0a2d9f2fc5f3e3284b9b85af9eda404 /src | |
| parent | 314c4c3ed632c5ce090a56c484e1a2d926f54ece (diff) | |
rambi: configure USBPHY_COMPBG by the setting in devicetree.cb
USBPHY_COMPBG needs to be configured by project
BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
checked the USBPHY_COMPBG is configured properly
CQ-DEPEND=CL:208557
Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208731
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75
Reviewed-on: http://review.coreboot.org/8217
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/google/rambi/devicetree.cb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 4f0a016cbe..5914a62608 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -22,6 +22,7 @@ chip soc/intel/baytrail register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" register "usb2_per_port_lane3" = "0x00049a09" register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + register "usb2_comp_bg" = "0x4700" # LPE audio codec settings register "lpe_codec_clk_freq" = "25" # 25MHz clock |