diff options
author | Raul E Rangel <rrangel@chromium.org> | 2021-02-05 16:50:28 -0700 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2021-02-11 16:35:13 +0000 |
commit | e0936a56ec27a75486743d524958fb34b6f9e896 (patch) | |
tree | d11bc76a90c811af03c0bb262373e974e233cf2f /src | |
parent | be35a3a012d61fad2ecfce9d1f5eb97e58942414 (diff) |
mb/amd/majolica: Add chromeos support
This change enables vboot support. To use it add CHROMEOS=y to your
config.
TEST=Boot majolica and see verstage run, and then see depthcharge load.
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 verstage starting (log level: 8)...
Phase 1
FMAP: area GBB found @ 805000 (458752 bytes)
VB2:vb2_check_recovery() Recovery reason from previous boot: 0x0 / 0x0
Phase 2
Phase 3
FMAP: area GBB found @ 805000 (458752 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_keyblock() Checking keyblock signature...
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
FMAP: area VBLOCK_A found @ 30000 (8192 bytes)
VB2:vb2_verify_fw_preamble() Verifying preamble.
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Phase 4
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
VB2:vb2api_init_hash() HW crypto forbidden by TPM flag, using SW
VB2:vb2_verify_digest() HW RSA forbidden, using SW
VB2:vb2_rsa_verify_digest() HW modexp forbidden, using SW
Saving secdata firmware
Saving secdata kernel
Saving nvdata
Slot A is selected
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: mcache @0x02017000 built for 9 files, used 0x1ec of 0x800 bytes
CBFS: Found 'fallback/romstage' @0x0 size 0x753c in mcache @0x02017000
BS: verstage times (exec / console): total (unknown) / 116 ms
coreboot-4.13-1730-g881092709a5e Fri Feb 5 23:50:28 UTC 2021 romstage starting (log level: 8)...
Family_Model: 00a50f00
FMAP: area FW_MAIN_A found @ 32000 (3137280 bytes)
CBFS: Found 'fspm.bin' @0x15440 size 0x2257d in mcache @0x02017138
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I43f0c6e33649332057f41f8813a86571b06032f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/amd/majolica/Kconfig | 15 | ||||
-rw-r--r-- | src/mainboard/amd/majolica/chromeos.fmd | 40 |
2 files changed, 45 insertions, 10 deletions
diff --git a/src/mainboard/amd/majolica/Kconfig b/src/mainboard/amd/majolica/Kconfig index ef0aa2048b..6f3f93ba30 100644 --- a/src/mainboard/amd/majolica/Kconfig +++ b/src/mainboard/amd/majolica/Kconfig @@ -7,6 +7,7 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select SOC_AMD_CEZANNE select AMD_SOC_CONSOLE_UART + select MAINBOARD_HAS_CHROMEOS config FMDFILE string @@ -21,6 +22,7 @@ config MAINBOARD_PART_NUMBER config AMD_FWM_POSITION_INDEX int + default 3 if CHROMEOS default 4 help TODO: might need to be adapted for better placement of files in cbfs @@ -37,4 +39,17 @@ config MAJOLICA_MCHP_FW_FILE The EC firmware blob is usually the first 128kByte of the stock firmware image. +config VBOOT + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_STARTS_IN_BOOTBLOCK + +config VBOOT_VBNV_OFFSET + hex + default 0x2A + +config CHROMEOS + # Use default libpayload config + select LP_DEFCONFIG_OVERRIDE if PAYLOAD_DEPTHCHARGE + endif # BOARD_AMD_MAJOLICA diff --git a/src/mainboard/amd/majolica/chromeos.fmd b/src/mainboard/amd/majolica/chromeos.fmd index 90cf2eb879..bb21767c31 100644 --- a/src/mainboard/amd/majolica/chromeos.fmd +++ b/src/mainboard/amd/majolica/chromeos.fmd @@ -1,14 +1,34 @@ FLASH@0xFF000000 16M { - BIOS { + SI_BIOS { EC 128K - RW_MRC_CACHE 64K - RW_LEGACY(CBFS) 4K - FW_MAIN_A(CBFS) 1M - VBLOCK_A 8K - FW_MAIN_B(CBFS) 1M - VBLOCK_B 8K - SHARED_DATA 8K - FMAP 4K - COREBOOT(CBFS) + RW_MRC_CACHE(PRESERVE) 64K + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 256 + } + RW_SECTION_B 3M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 256 + } + RW_ELOG(PRESERVE) 4K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 20K + SMMSTORE(PRESERVE) 4K + RW_LEGACY(CBFS) + WP_RO@8M 8M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 448K + COREBOOT(CBFS) + } + } } } |