diff options
| author | Maximilian Brune <maximilian.brune@9elements.com> | 2022-08-25 14:22:47 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-08-29 22:52:36 +0000 |
| commit | e01e9b83f901aeb636b1d891c8cd3dbeee0dfcca (patch) | |
| tree | d92286d8e9207cc3fa8257135fe744671d47ce5c /src | |
| parent | 2dd74906e4830d86a4e4a8113788e8a5c92de2ee (diff) | |
mb/prodrive/atlas: Fix SMBUS/SPD addresses
Commit 0e7cf3d81d121181a94b6a594b944628c2e5a939 (soc/intel/alderlake:
Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5
SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the
SoC code bug required commit 044883615d4471b7a0b883eb8b8224d95faf52af
(mb/prodrive/atlas: Update correct SPD address) so that at least some
RAM would work. Now that the SoC code bug is fixed, the workaround is
no longer needed, so use the correct SPD address mapping.
TEST=Boot Atlas and verify that both memory channels work
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/prodrive/atlas/romstage_fsp_params.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/mainboard/prodrive/atlas/romstage_fsp_params.c b/src/mainboard/prodrive/atlas/romstage_fsp_params.c index 8aaef5bdfd..5afbab071a 100644 --- a/src/mainboard/prodrive/atlas/romstage_fsp_params.c +++ b/src/mainboard/prodrive/atlas/romstage_fsp_params.c @@ -35,9 +35,11 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) const struct mem_spd dimm_module_spd_info = { .topo = MEM_TOPO_DIMM_MODULE, .smbus = { - [3] = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { .addr_dimm[0] = 0x52, - .addr_dimm[1] = 0x53, }, }, }; |