diff options
| author | Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com> | 2021-07-23 15:56:15 +0800 |
|---|---|---|
| committer | Hung-Te Lin <hungte@chromium.org> | 2021-07-28 02:51:36 +0000 |
| commit | de3859d53856b7fcbc32df897a6afa5144e743ff (patch) | |
| tree | c875d3a4d018ec3b0ad59eec9431b477f2d66803 /src | |
| parent | 403fa86924157b5fd73365b41803698602a168a1 (diff) | |
vc/mediatek/mt8195: Improve DRAM stability by impedance tracking
Enable the impedance tracking for channel 2 and channel 3.
The impedance tracking can compensate the settings of impedance
when the temperature changes.
Signed-off-by: Ryan Chuang <ryan.chuang@mediatek.corp-partner.google.com>
Change-Id: I047ab70bb59736a8ba8ae75ab15659900c784342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c index 187fb0db4f..f3fc126cc8 100644 --- a/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c +++ b/src/vendorcode/mediatek/mt8195/dramc/dramc_tracking.c @@ -1373,7 +1373,11 @@ void DramcImpedanceTrackingEnable(DRAMC_CTX_T *p) if (channel_num_auxadc > 2) { vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(1, MISC_IMPCAL_DIS_SUS_CH1_DRV)); vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_DIS_SUS_CH0_DRV) | P_Fld(0, MISC_IMPCAL_DIS_SUS_CH1_DRV)); - } + vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHC_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x0, MISC_CTRL0_IMPCAL_TRACK_DISABLE)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_CTRL0 + SHIFT_TO_CHD_ADDR, P_Fld(0x1, MISC_CTRL0_IMPCAL_LP_ECO_OPT) | P_Fld(0x1, MISC_CTRL0_IMPCAL_TRACK_DISABLE)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHC_ADDR, P_Fld(0, MISC_IMPCAL_IMPSRCEXT) | P_Fld(1, MISC_IMPCAL_IMPCAL_ECO_OPT)); + vIO32WriteFldMulti(DDRPHY_REG_MISC_IMPCAL + SHIFT_TO_CHD_ADDR, P_Fld(1, MISC_IMPCAL_IMPSRCEXT) | P_Fld(0, MISC_IMPCAL_IMPCAL_ECO_OPT)); + } #endif //Maoauo: keep following setting for SPMFW enable REFCTRL0_DRVCGWREF = 1 (Imp SW Save mode) |