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authorZanxi Chen <chenzanxi@huaqin.corp-partner.google.com>2021-03-18 21:54:57 +0800
committerPatrick Georgi <pgeorgi@google.com>2021-03-22 11:22:06 +0000
commitd92966b61046bb78f2d025b61287e32d3f44b61a (patch)
treefd7f7a940b02ee9bfc1234a679e5abfa19518559 /src
parent61fcb7e9654634cfe0c8a7bf56581fb54d943bd8 (diff)
mb/google/dedede/var/storo: Add USB Port Configuration
Add USB Port configuration into devicetree for storo BUG=b:177389444 BRANCH=dedede TEST=built firmware and verified USB3.0 function is OK Change-Id: I1527c7178ffac9b2322eb65aab6e2086d949e47c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/dedede/variants/storo/overridetree.cb1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/google/dedede/variants/storo/overridetree.cb b/src/mainboard/google/dedede/variants/storo/overridetree.cb
index 0780f57a39..0025fece98 100644
--- a/src/mainboard/google/dedede/variants/storo/overridetree.cb
+++ b/src/mainboard/google/dedede/variants/storo/overridetree.cb
@@ -2,6 +2,7 @@ chip soc/intel/jasperlake
# USB Port Configuration
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # User Facing Camera
+ register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1
# Intel Common SoC Config
#+-------------------+---------------------------+