diff options
| author | John Zhao <john.zhao@intel.com> | 2021-05-19 15:33:35 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-05-26 15:43:01 +0000 |
| commit | d8bb05ade0719c31668bb153e3aea2017688a36a (patch) | |
| tree | f2463abac817659e2b220f0967e1890c11abd1b8 /src | |
| parent | cf2c99f40ca47b8c066e2eac3a873e7b45d03947 (diff) | |
soc/intel/tigerlake: Add validity for TBT firmware authentication
After Thunderbolt firmware is downloaded to IMR, its authentication
validity needs to be checked. This change adds the TBT firmware IMR
status register offset and its authentication valid bit for
valid_tbt_auth function usage.
BUG=b:188695995
TEST=Built Voxel coreboot image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia25827f18a10bf4d2dcabfe81565ac326851af3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54709
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/tigerlake/include/soc/tcss.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/soc/intel/tigerlake/include/soc/tcss.h b/src/soc/intel/tigerlake/include/soc/tcss.h index 713528bdbb..014e3076e6 100644 --- a/src/soc/intel/tigerlake/include/soc/tcss.h +++ b/src/soc/intel/tigerlake/include/soc/tcss.h @@ -3,6 +3,10 @@ #ifndef _SOC_TCSS_H_ #define _SOC_TCSS_H_ +/* Thunderbolt firmware IMR status */ +#define IOM_CSME_IMR_TBT_STATUS 0x14 +#define TBT_VALID_AUTHENTICATION (1 << 30) + /* IOM aux bias control registers in REGBAR MMIO space */ #define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 0x1070 #define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x) (IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4) |