diff options
author | Subrata Banik <subratabanik@google.com> | 2022-02-16 19:34:52 +0530 |
---|---|---|
committer | Felix Held <felix-coreboot@felixheld.de> | 2022-02-18 14:56:33 +0000 |
commit | d55a08242b89e12241da70dbd564e2acf2aada57 (patch) | |
tree | 157040d11196a40bd7bc5f9fd1b7d3757de1a11d /src | |
parent | f04faa149ffe4df7dd18391aa4e2eae9a6ceec73 (diff) |
mb/google/brya/var/taniks: Use ACPI _PLD macro
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r-- | src/mainboard/google/brya/variants/taniks/overridetree.cb | 24 |
1 files changed, 16 insertions, 8 deletions
diff --git a/src/mainboard/google/brya/variants/taniks/overridetree.cb b/src/mainboard/google/brya/variants/taniks/overridetree.cb index 462e367cb1..f80f5d67fc 100644 --- a/src/mainboard/google/brya/variants/taniks/overridetree.cb +++ b/src/mainboard/google/brya/variants/taniks/overridetree.cb @@ -396,13 +396,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref tcss_usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port3 on probe DB_USB DB_USB3_WITH_A end @@ -416,13 +418,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C0 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(1, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" device ref usb2_port1 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-C Port C1 (DB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" - register "group" = "ACPI_PLD_GROUP(2, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port3 on probe DB_USB DB_USB3_WITH_A end @@ -436,7 +440,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (DB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb2_port7 on probe DB_USB DB_USB3_WITH_A end @@ -444,7 +449,8 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port (MLB)"" register "type" = "UPC_TYPE_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb2_port9 on end end chip drivers/usb/acpi @@ -457,13 +463,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (MLB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(4, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(4, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A Port (DB)"" register "type" = "UPC_TYPE_USB3_A" - register "group" = "ACPI_PLD_GROUP(3, 1)" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" device ref usb3_port3 on probe DB_USB DB_USB3_WITH_A end |