diff options
| author | sowmyav <v.sowmya@intel.com> | 2017-03-02 10:09:59 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-10 11:19:04 +0100 |
| commit | d448a5e98bab6942301032146b5cb0fe5625d496 (patch) | |
| tree | fb116d6b0008432bee9b300f1e3522d5a1da80b0 /src | |
| parent | 6e53ae6f5c12b70c2a86370f0dd9df37a12c8118 (diff) | |
soc/intel/skylake:Add _DSM method to reduce D3 cold delay for eMMC controller
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Skylake systems like Cave and Caroline.
This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.
BUG=b:35774937
BRANCH=none
TEST=update caroline coreboot and test i/o latency is under 100ms
Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/18532
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/skylake/acpi/scs.asl | 43 |
1 files changed, 43 insertions, 0 deletions
diff --git a/src/soc/intel/skylake/acpi/scs.asl b/src/soc/intel/skylake/acpi/scs.asl index aea4483473..1f89689fb7 100644 --- a/src/soc/intel/skylake/acpi/scs.asl +++ b/src/soc/intel/skylake/acpi/scs.asl @@ -20,6 +20,7 @@ Device (EMMC) { Name (_ADR, 0x001E0004) Name (_DDN, "eMMC Controller") + Name (UUID, ToUUID ("E5C937D0-3553-4D7A-9117-EA4D19C3434D")) OperationRegion (EMCR, PCI_Config, 0x00, 0x100) Field (EMCR, DWordAcc, NoLock, Preserve) @@ -31,6 +32,48 @@ Device (EMMC) PGEN, 1, /* PG_ENABLE */ } + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 9: Device Readiness Durations + * Returns a package of five integers covering + * various device related delay in PCIe Base Spec. + */ + If (LEqual (Arg2, 9)) { + /* + * Function 9 support for revision 3. + * ECN link for function definitions + * [https://pcisig.com/sites/default/files/ + * specification_documents/ + * ECN_fw_latency_optimization_final.pdf] + */ + If (LEqual (Arg1, 3)) { + /* + * Integer 0: FW reset time. + * Integer 1: FW data link up time. + * Integer 2: FW functional level reset + * time. + * Integer 3: FW D3 hot to D0 time. + * Integer 4: FW VF enable time. + * set ACPI constant Ones for elements + * where overriding the default value + * is not desired. + */ + Return (Package (5) {0, Ones, Ones, + Ones, Ones}) + } + } + } + Return (Buffer() { 0x00 }) + } + Method (_PS0, 0, Serialized) { /* Disable Power Gate */ |