diff options
| author | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2021-03-17 15:13:08 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-03-28 16:00:32 +0000 |
| commit | d1150fd6d76e76fd1ccf8ede0ca96de0c404073c (patch) | |
| tree | 1685cfb799e8144effe15079146af75a1aa8d270 /src | |
| parent | 5052e1f45cd1fcffa6f3814bd96a98d52a98b865 (diff) | |
mb/intel/adlrvp: Enable CSE Lite SKU
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST= Built and booted on ADL-P LP4 RVP
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
| -rw-r--r-- | src/mainboard/intel/adlrvp/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index a359d62145..c1c45868ae 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -17,6 +17,7 @@ config BOARD_SPECIFIC_OPTIONS select SOC_INTEL_ALDERLAKE_PCH_M if BOARD_INTEL_ADLRVP_M || BOARD_INTEL_ADLRVP_M_EXT_EC select HAVE_SPD_IN_CBFS select DRIVERS_SOUNDWIRE_ALC711 + select SOC_INTEL_CSE_LITE_SKU config CHROMEOS select GBB_FLAG_FORCE_DEV_SWITCH_ON |