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authorLawrence Chang <lawrence.chang@intel.corp-partner.google.com>2022-11-22 21:33:26 +0800
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2022-12-02 03:11:41 +0000
commitcab2c53e3cabb16d662dc45c43c141e2d9a89ce9 (patch)
tree191e7bb54379b915fcda09949b7b1ea358c9a076 /src
parent69cab3a0446acae01e0ed09ea1304878e1aa9bc6 (diff)
mb/google/nissa/var/xivu: Fine-tune eMMC DLL
Fine-tune eMMC DLL based on Xivu EVT system. BUG=b:256538132 TEST=executed 3000 cycles of cold boot successfully Change-Id: Iaa8338fd0faa0e01f42ee77dea135c7a241ed3be Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69892 Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/variants/xivu/overridetree.cb45
1 files changed, 45 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/xivu/overridetree.cb b/src/mainboard/google/brya/variants/xivu/overridetree.cb
index ac23c68517..bfaa639f41 100644
--- a/src/mainboard/google/brya/variants/xivu/overridetree.cb
+++ b/src/mainboard/google/brya/variants/xivu/overridetree.cb
@@ -16,6 +16,51 @@ end
chip soc/intel/alderlake
register "sagv" = "SaGv_Enabled"
+ # EMMC Tx CMD Delay
+ # Refer to EDS-Vol2-42.3.7.
+ # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
+ # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
+ register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x00000505"
+
+ # EMMC TX DATA Delay 1
+ # Refer to EDS-Vol2-42.3.8.
+ # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
+ # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x00000a12"
+
+ # EMMC TX DATA Delay 2
+ # Refer to EDS-Vol2-42.3.9.
+ # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
+ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
+ # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1c292828"
+
+ # EMMC RX CMD/DATA Delay 1
+ # Refer to EDS-Vol2-42.3.10.
+ # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
+ # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
+ # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
+ # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
+ register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1c175a3b"
+
+ # EMMC RX CMD/DATA Delay 2
+ # Refer to EDS-Vol2-42.3.12.
+ # [17:16] stands for Rx Clock before Output Buffer,
+ # 00: Rx clock after output buffer,
+ # 01: Rx clock before output buffer,
+ # 10: Automatic selection based on working mode.
+ # 11: Reserved
+ # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
+ # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
+ register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x00010023"
+
+ # EMMC Rx Strobe Delay
+ # Refer to EDS-Vol2-42.3.11.
+ # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
+ # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
+ register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x00011111"
+
# Disable CNVi BT
register "cnvi_bt_core" = "false"