diff options
| author | Johnny Lin <johnny_lin@wiwynn.com> | 2021-01-25 15:00:48 +0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-01-28 09:30:09 +0000 |
| commit | ca083db4d377cdfeca61ad97b33efadc0f9ccf36 (patch) | |
| tree | 8f23791d88861dc29227ac6a998ad7e3bf8232bb /src | |
| parent | d92d7cb515aa1222d2b8e500157d4b911d7c8783 (diff) | |
xeon_sp/cpx: Update meminfo max_capacity_mib and number_of_devices
The values can be used during SMBIOS type 16 creation.
Tested=On OCP Delta Lake, dmidecode -t 16 to verify.
Handle 0x000A, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: Single-bit ECC
Maximum Capacity: 1146 GB
Error Information Handle: Not Provided
Number Of Devices: 6
Change-Id: Id8f92dc96a7a3eb2e6db330adda98a7fe6d516c8
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src')
| -rw-r--r-- | src/soc/intel/xeon_sp/cpx/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index e423d0a6d1..6025f2a6d0 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -60,6 +60,9 @@ void save_dimm_info(void) return; } memset(mem_info, 0, sizeof(*mem_info)); + /* According to Dear Customer Letter it's 1.12 TB per processor. */ + mem_info->max_capacity_mib = 1.12 * MiB * CONFIG_MAX_SOCKET; + mem_info->number_of_devices = CONFIG_DIMM_MAX; dimm_max = ARRAY_SIZE(mem_info->dimm); vdd_voltage = get_ddr_voltage(hob->DdrVoltage); /* For now only implement for one socket and hard-coded for DDR4 */ |