soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init

FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize
& tear down Cache-As-Ram.  Add TempRamInit & TempRamExit usage to
ApolloLake SoC when CONFIG_FSP_CAR is enabled.

Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram
is correctly set up and torn down using the FSP v2.0 APIs
without coreboot implementation of CAR init/teardown.

Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/17063
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

4 files changed, 173 insertions, 4 deletions

diff --git a/src/arch/x86/exit_car.S b/src/arch/x86/exit_car.S
index 5c62c92af8..61287d2597 100644
--- a/src/arch/x86/exit_car.S
+++ b/src/arch/x86/exit_car.S
@@ -19,7 +19,8 @@
 
 .section ".module_parameters", "aw", @progbits
 /* stack_top indicates the stack to pull MTRR information from. */
-stack_top:
+.global post_car_stack_top
+post_car_stack_top:
 .long	0
 .long	0
 
@@ -38,7 +39,7 @@ _start:
 	invd
 
 	/* Set up new stack. */
-	mov	stack_top, %esp
+	mov	post_car_stack_top, %esp
 
 	/*
 	 * Honor variable MTRR information pushed on the stack with the
diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc
index d058ddbbba..5a65f43485 100644
--- a/src/soc/intel/apollolake/Makefile.inc
+++ b/src/soc/intel/apollolake/Makefile.inc
@@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc
 subdirs-y += ../../../cpu/x86/cache
 
 bootblock-y += bootblock/bootblock.c
-bootblock-y += bootblock/cache_as_ram.S
 bootblock-y += bootblock/bootblock.c
 bootblock-y += car.c
 bootblock-y += flash_ctrlr.c
@@ -23,6 +22,12 @@ bootblock-y += spi.c
 bootblock-y += tsc_freq.c
 bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 
+ifeq ($(CONFIG_FSP_CAR),y)
+bootblock-y += bootblock/cache_as_ram_fsp.S
+else
+bootblock-y += bootblock/cache_as_ram.S
+endif
+
 romstage-y += car.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c
 romstage-y += flash_ctrlr.c
@@ -79,7 +84,6 @@ ramstage-y += sram.c
 ramstage-y += spi.c
 ramstage-y += xhci.c
 
-postcar-y += exit_car.S
 postcar-y += flash_ctrlr.c
 postcar-y += memmap.c
 postcar-y += mmap_boot.c
@@ -87,6 +91,12 @@ postcar-y += spi.c
 postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 postcar-y += tsc_freq.c
 
+ifeq ($(CONFIG_FSP_CAR),y)
+postcar-y += exit_car_fsp.S
+else
+postcar-y += exit_car.S
+endif
+
 verstage-y += car.c
 verstage-y += flash_ctrlr.c
 verstage-y += i2c_early.c
diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
new file mode 100644
index 0000000000..f55582a706
--- /dev/null
+++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015-2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <device/pci_def.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/cr.h>
+#include <cpu/x86/post_code.h>
+#include <soc/cpu.h>
+
+#include <../../../arch/x86/walkcbfs.S>
+
+#define FSP_HDR_OFFSET 0x94
+
+.global	bootblock_pre_c_entry
+bootblock_pre_c_entry:
+
+.global	cache_as_ram
+cache_as_ram:
+	post_code(0x21)
+
+	/* find fsp in cbfs */
+	lea	fsp_name, %esi
+	mov	$1f, %esp
+	jmp	walkcbfs_asm
+1:
+	cmp	$0, %eax
+	jz	.halt_forever
+	mov	CBFS_FILE_OFFSET(%eax), %ebx
+	bswap	%ebx
+	add	%eax, %ebx
+	add	FSP_HDR_OFFSET, %ebx
+
+	/*
+	 * ebx = FSP INFO HEADER
+	 * Calculate entry into FSP
+	 */
+	mov	0x30(%ebx), %eax	/* Load TempRamInitEntryOffset */
+	add	0x1c(%ebx), %eax	/* add the FSP ImageBase */
+
+	/*
+	 * Pass early init variables on a fake stack (no memory yet)
+	 * as well as the return location
+	 */
+	lea	CAR_init_stack, %esp
+
+	/* call FSP binary to setup temporary stack */
+	jmp	*%eax
+
+/*
+ * If the TempRamInit API is successful, then when returning, the ECX and
+ * EDX registers will point to the temporary but writeable memory range
+ * available to the bootloader where ECX is the start and EDX is the end of
+ * the range i.e. [ECX,EDX).  See Apollo Lake FSP Integration Guide for more
+ * information.
+ *
+ * Return Values:
+ * EAX | Return Status
+ * ECX | Temporary Memory Start
+ * EDX | Temporary Memory End
+ * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call
+ */
+
+CAR_init_done:
+
+	/* Setup bootblock stack */
+	mov	%edx, %esp
+
+	/* clear CAR_GLOBAL area as it is not shared */
+	cld
+	xor	%eax, %eax
+	movl	$(_car_global_end), %ecx
+	movl	$(_car_global_start), %edi
+	sub	%edi, %ecx
+	rep	stosl
+
+	/* We can call into C functions now */
+	call	bootblock_c_entry
+
+	/* Never reached */
+
+.halt_forever:
+	post_code(POST_DEAD_CODE)
+	hlt
+	jmp	.halt_forever
+
+CAR_init_params:
+	.long	0                                 /* Microcode Location */
+	.long	0                                 /* Microcode Length */
+	.long	0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */
+	.long	CONFIG_ROM_SIZE                  /* Total Firmware Length */
+
+CAR_init_stack:
+	.long	CAR_init_done
+	.long	CAR_init_params
+
+fsp_name:
+	.ascii	"blobs/fspt.bin\x00"
diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S
new file mode 100644
index 0000000000..32c276c5eb
--- /dev/null
+++ b/src/soc/intel/apollolake/exit_car_fsp.S
@@ -0,0 +1,47 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/cr.h>
+#include <soc/cpu.h>
+
+/*
+ * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed.
+ * This version of chipset_teardown_car sets up the stack, then bypasses
+ * the rest of arch/x86/exit_car.S and calls main() itself instead of
+ * returning to _start. In main(), the TempRamExit FSP API is called
+ * to tear down the CAR and set up caching which can be overwritten
+ * after the API call.  More info can be found in the Apollo Lake FSP
+ * Integration Guide included with the FSP binary.  The below
+ * caching settings are based on an 8MiB Flash Size given as a
+ * parameter to TempRamInit.
+ *
+ * 	TempRamExit MTRR Settings:
+ * 	0x00000000  - 0x0009FFFF           | Write Back
+ * 	0x000C0000  - Top of Low Memory    | Write Back
+ * 	0xFF800000  - 0xFFFFFFFF Flash Reg | Write Protect
+ * 	0x100000000 - Top of High Memory   | Write Back
+ */
+
+.text
+.global chipset_teardown_car
+chipset_teardown_car:
+
+	/* Set up new stack. */
+	mov	post_car_stack_top, %esp
+
+	/* Call C code */
+	call	main