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authorIan Feng <ian_feng@compal.corp-partner.google.com>2021-11-29 14:27:11 +0800
committerFelix Held <felix-coreboot@felixheld.de>2021-12-03 21:18:37 +0000
commitc75d846971c2fd96c989a7f8a14011bb70866409 (patch)
treefb4c737f305329fae2e62eb3ec8359d37bcccc77 /src
parent0f42e5e8f16bcd0ee1e853e095e7975762aafbc1 (diff)
mb/google/brya/var/felwinter: Add WiFi SAR table for felwinter
Add WiFi SAR table for felwinter. BUG=b:206901900 TEST=emerge-brya chromeos-config chromeos-config-bsp-private coreboot-private-files-baseboard-brya coreboot chromeos-bootimage and checked SAR table can load by WiFi driver. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src')
-rw-r--r--src/mainboard/google/brya/Kconfig.name1
-rw-r--r--src/mainboard/google/brya/variants/felwinter/variant.c6
2 files changed, 7 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name
index cd00815afb..ead3348d91 100644
--- a/src/mainboard/google/brya/Kconfig.name
+++ b/src/mainboard/google/brya/Kconfig.name
@@ -108,6 +108,7 @@ config BOARD_GOOGLE_FELWINTER
bool "-> Felwinter"
select BOARD_GOOGLE_BASEBOARD_BRYA
select DRIVERS_GENERIC_GPIO_KEYS
+ select CHROMEOS_WIFI_SAR if CHROMEOS
config BOARD_GOOGLE_ANAHERA
bool "-> Anahera"
diff --git a/src/mainboard/google/brya/variants/felwinter/variant.c b/src/mainboard/google/brya/variants/felwinter/variant.c
index ee39ef080e..8b270de04e 100644
--- a/src/mainboard/google/brya/variants/felwinter/variant.c
+++ b/src/mainboard/google/brya/variants/felwinter/variant.c
@@ -3,6 +3,12 @@
#include <chip.h>
#include <fw_config.h>
#include <baseboard/variants.h>
+#include <sar.h>
+
+const char *get_wifi_sar_cbfs_filename(void)
+{
+ return "wifi_sar_0.hex";
+}
void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config)
{